公开(公告)号：US20220269487A1

公开(公告)日：2022-08-25

申请号：US17180993

申请日：2021-02-22

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72 ,  G06F21/60

Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.

公开(公告)号：US20220269488A1

公开(公告)日：2022-08-25

申请号：US17180999

申请日：2021-02-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72 ,  G06F21/60

Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.

公开(公告)号：US12079594B2

公开(公告)日：2024-09-03

申请号：US17180999

申请日：2021-02-22

Applicant: Mellanox Technologies, Ltd.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72 ,  G06F21/60

CPC classification number: G06F7/728 ,  G06F21/602

Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.

公开(公告)号：US20240406148A1

公开(公告)日：2024-12-05

申请号：US18626354

申请日：2024-04-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Uria Basher ,  Michael Tahar ,  Amir Modan ,  Ben Witulski ,  Miriam Menes ,  Miri Shtaif

IPC: H04L9/40

Abstract: In one embodiment, a system includes a networking device including a network interface to receive network packets having headers including datagram transport layer security (DTLS) headers from a remote device over a packet data network, packet processing circuitry to identify first packets of the received packets for DTLS processing in the packet processing circuitry, identify second packets of the received packets to bypass DTLS processing in the packet processing circuitry and to be provided to software to perform DTLS processing on the second packets, and perform DTLS processing on the first packets, and a host interface to provide the DTLS processed first packets to the software, and provide the second packets to the software to perform DTLS processing on the second packets.

公开(公告)号：US12131132B2

公开(公告)日：2024-10-29

申请号：US17180993

申请日：2021-02-22

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adir Zevulun ,  Uria Basher ,  Nir Shmuel ,  Ben Witulski

IPC: G06F7/72

CPC classification number: G06F7/728

Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.