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    Network device with datagram transport layer security selective software offload
    1.
    发明申请
    Network device with datagram transport layer security selective software offload 有权

    公开(公告)号：US20240406148A1

    公开(公告)日：2024-12-05

    申请号：US18626354

    申请日：2024-04-04

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Uria Basher ,  Michael Tahar ,  Amir Modan ,  Ben Witulski ,  Miriam Menes ,  Miri Shtaif

    IPC: H04L9/40

    Abstract: In one embodiment, a system includes a networking device including a network interface to receive network packets having headers including datagram transport layer security (DTLS) headers from a remote device over a packet data network, packet processing circuitry to identify first packets of the received packets for DTLS processing in the packet processing circuitry, identify second packets of the received packets to bypass DTLS processing in the packet processing circuitry and to be provided to software to perform DTLS processing on the second packets, and perform DTLS processing on the first packets, and a host interface to provide the DTLS processed first packets to the software, and provide the second packets to the software to perform DTLS processing on the second packets.

    Packet switch with reduced latency
    3.
    发明授权
    Packet switch with reduced latency 有权

    公开(公告)号：US10462075B2

    公开(公告)日：2019-10-29

    申请号：US15470940

    申请日：2017-03-28

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

    IPC: H04L12/879 ,  H04L12/861

    Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

    Caching Policy In A Multicore System On A Chip (SOC)
    4.
    发明申请
    Caching Policy In A Multicore System On A Chip (SOC) 审中-公开

    公开(公告)号：US20180349292A1

    公开(公告)日：2018-12-06

    申请号：US15610823

    申请日：2017-06-01

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Gilad Tal ,  Gil Moran ,  Miriam Menes ,  Gil Kopilov ,  Shlomo Raikin

    IPC: G06F12/123 ,  G06F12/0808

    Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected access profile from plural access profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected access profile for a selected least recently used (LRU) position in the cache.

    Packet switch with reduced latency
    5.
    发明授权
    Packet switch with reduced latency 有权

    公开(公告)号：US09641465B1

    公开(公告)日：2017-05-02

    申请号：US13972968

    申请日：2013-08-22

    Applicant: Mellanox Technologies Ltd.

    Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

    IPC: H04L12/861

    CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9094

    Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

    Confidential computing with device memory isolation
    6.
    发明授权
    Confidential computing with device memory isolation 有权

    公开(公告)号：US12259963B2

    公开(公告)日：2025-03-25

    申请号：US17676890

    申请日：2022-02-22

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Boris Pismenny ,  Miriam Menes ,  Ahmad Atamli ,  Ilan Pardo ,  Ariel Shahar ,  Uria Basher

    IPC: G06F21/53 ,  G06F9/50 ,  G06F13/28 ,  G06F21/79

    Abstract: A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.

    Cryptographic data communication apparatus
    7.
    发明授权
    Cryptographic data communication apparatus 有权

    公开(公告)号：US11909855B2

    公开(公告)日：2024-02-20

    申请号：US18075460

    申请日：2022-12-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

    IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

    CPC classification number: H04L9/0625 ,  H04L9/0861 ,  H04L9/3247

    Abstract: In one embodiment, data communication apparatus includes packet processing circuitry to receive data from a memory responsively to a data transfer request, and cryptographically process the received data in units of data blocks using a block cipher so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including respective ones of the cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of respective one of the packets, such that respective ones of the cryptographically processed data blocks are divided into two respective segments, which are contained in successive respective ones of the packets in the sequence, and a network interface which includes one or more ports for connection to a packet data network and is configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports.

    Unique address assignment without reconfiguration
    8.
    发明公开
    Unique address assignment without reconfiguration 审中-公开

    公开(公告)号：US20240015130A1

    公开(公告)日：2024-01-11

    申请号：US17859022

    申请日：2022-07-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Eitan Zahavi ,  Guy Rozenberg ,  Matty Kadosh ,  Lion Levi ,  Boris Pismenny ,  Alex Netes ,  Miriam Menes ,  Lior Hodaya Bezen ,  Michael Tahar

    IPC: H04L61/106 ,  H04L61/5092 ,  H04L61/5061

    CPC classification number: H04L61/106 ,  H04L61/5092 ,  H04L61/5061

    Abstract: A method for communication includes provisioning each node in a network with a respective set of two or more network addresses. Each node in succession is assigned a respective network address from the respective provisioned set that has not been assigned for use by any preceding node. Upon finding for a given node that all the network addresses in the respective provisioned set were assigned to preceding nodes, the preceding nodes are searched to identify a candidate node having an additional network address in the respective provisioned set, other than the assigned respective network address, that was not yet assigned to any of the nodes. The additional network address is assigned to the candidate node instead of the respective network address that was previously assigned to the candidate node, and the assigning of the network addresses to the nodes in the succession resumes following the candidate node.

    PACKET SWITCH WITH REDUCED LATENCY
    10.
    发明申请
    PACKET SWITCH WITH REDUCED LATENCY 审中-公开

    公开(公告)号：US20170201468A1

    公开(公告)日：2017-07-13

    申请号：US15470940

    申请日：2017-03-28

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

    IPC: H04L12/879 ,  H04L12/861

    CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9094

    Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

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