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公开(公告)号：US12259963B2
公开(公告)日：2025-03-25
申请号：US17676890
申请日：2022-02-22
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Boris Pismenny , Miriam Menes , Ahmad Atamli , Ilan Pardo , Ariel Shahar , Uria Basher
Abstract: A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.
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公开(公告)号：US20220269487A1
公开(公告)日：2022-08-25
申请号：US17180993
申请日：2021-02-22
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Adir Zevulun , Uria Basher , Nir Shmuel , Ben Witulski
Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.
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公开(公告)号：US11726666B2
公开(公告)日：2023-08-15
申请号：US17372466
申请日：2021-07-11
Applicant: Mellanox Technologies, Ltd.
Inventor： Ben Ben-Ishay , Boris Pismenny , Yorai Itzhak Zack , Khalid Manaa , Liran Liss , Uria Basher , Or Gerlitz , Miriam Menes
IPC: G06F12/00 , G06F3/06 , H04L1/00 , H04L1/1867
CPC classification number: G06F3/0619 , G06F3/067 , G06F3/0611 , G06F3/0659 , G06F3/0679 , H04L1/0041 , H04L1/0045 , H04L1/189
Abstract: A network adapter includes a network interface controller and a processor. The network interface controller is to communicate over a peripheral bus with a host, and over a network with a remote storage device. The processor is to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive first I/O transactions of the bus storage protocol from the host, via the exposed peripheral-bus device, and to complete the first I/O transactions in the remote storage device by (i) translating between the first I/O transactions and second I/O transactions of a network storage protocol, and (ii) executing the second I/O transactions in the remote storage device. For receiving and completing the first I/O transactions, the processor is to cause the network interface controller to transfer data directly between the remote storage device and a memory of the host using zero-copy.
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公开(公告)号：US20220269488A1
公开(公告)日：2022-08-25
申请号：US17180999
申请日：2021-02-22
Applicant: Mellanox Technologies, Ltd.
Inventor： Adir Zevulun , Uria Basher , Nir Shmuel , Ben Witulski
Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.
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公开(公告)号：US10565339B2
公开(公告)日：2020-02-18
申请号：US16038207
申请日：2018-07-18
Applicant: Mellanox Technologies, Ltd.
Inventor： Uria Basher , Anton Rozen
IPC: G06F17/50
Abstract: A method for designing a logic circuit includes providing an initial design of the logic circuit, including at least first and second logic stages, and a sequential component, which is inserted between the first and second logic stages and comprises a flip-flop or a latch. Timing delays of multiple paths in the initial design, including at least one path in which the sequential component is bypassed, are estimated. Based on the timing delays, a decision is made whether the paths in which the sequential component is bypassed meet a timing constraint set for the logic circuit. A final design of the logic circuit is then generated, in which the sequential component is either bypassed or not bypassed, depending on the decision.
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Patent Agency Ranking
公开(公告)号：US12079594B2
公开(公告)日：2024-09-03
申请号：US17180999
申请日：2021-02-22
Applicant: Mellanox Technologies, Ltd.
Inventor： Adir Zevulun , Uria Basher , Nir Shmuel , Ben Witulski
CPC classification number: G06F7/728 , G06F21/602
Abstract: A Montgomery multiplication apparatus (MMA), for multiplying two multiplicands modulo a predefined number, includes a pre-compute circuit and a Montgomery multiplication circuit. The pre-compute circuit is configured to compute a Montgomery pre-compute value by performing a series of iterations. In a given iteration, the pre-compute circuit is configured to modify one or more intermediate values by performing bit-wise operations on the intermediate values calculated in a preceding iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands, modulo the predefined number, by performing a plurality of Montgomery reduction operations using the Montgomery pre-compute value computed by the pre-compute circuit.
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公开(公告)号：US20240202315A1
公开(公告)日：2024-06-20
申请号：US18084964
申请日：2022-12-20
Applicant: Mellanox Technologies, Ltd.
Inventor： Ahmad Atamli , Ilan Pardo , Miriam Menes , Shahaf Shuler , Meni Orenbach , Uria Basher
IPC: G06F21/53
CPC classification number: G06F21/53 , G06F2221/033
Abstract: The technology disclosed herein enables selective clearing of memory regions upon a context switch. An example method includes the operations of: receiving a memory access request referencing a memory region; determining an identifier of a current execution context associated with the memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, updating the metadata associated with the memory region to store the identifier of the current execution context; clearing at least a part of the memory region; and processing the memory access request with respect to the memory region.
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公开(公告)号：US20230010150A1
公开(公告)日：2023-01-12
申请号：US17372466
申请日：2021-07-11
Applicant: Mellanox Technologies, Ltd.
Inventor： Ben Ben-Ishay , Boris Pismenny , Yorai Itzhak Zack , Khalid Manaa , Liran Liss , Uria Basher , Or Gerlitz , Miriam Menes
Abstract: A network adapter includes a network interface controller and a processor. The network interface controller is to communicate over a peripheral bus with a host, and over a network with a remote storage device. The processor is to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive first I/O transactions of the bus storage protocol from the host, via the exposed peripheral-bus device, and to complete the first I/O transactions in the remote storage device by (i) translating between the first I/O transactions and second I/O transactions of a network storage protocol, and (ii) executing the second I/O transactions in the remote storage device. For receiving and completing the first I/O transactions, the processor is to cause the network interface controller to transfer data directly between the remote storage device and a memory of the host using zero-copy.
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公开(公告)号：US20240146703A1
公开(公告)日：2024-05-02
申请号：US18195615
申请日：2023-05-10
Applicant: Mellanox Technologies, Ltd.
Inventor： Yuval Shicht , Miriam Menes , Ariel Shahar , Uria Basher , Boris Pismenny
CPC classification number: H04L63/0485 , H04L9/0618 , H04L63/123
Abstract: A network device includes a hardware pipeline to process a network packet to be encrypted. A portion of the hardware pipeline retrieves information from the network packet and generates a command based on the information. A block cipher circuit is coupled inline within the hardware pipeline. The hardware pipeline includes hardware engines coupled between the portion of the hardware pipeline and the block cipher circuit. The hardware engines parse and execute the command to determine a set of inputs and input the set of inputs and portions of the network packet to the block cipher circuit. The block cipher circuit encrypts a payload data of the network packet based on the set of inputs.
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公开(公告)号：US20230267196A1
公开(公告)日：2023-08-24
申请号：US17676890
申请日：2022-02-22
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Boris Pismenny , Miriam Menes , Ahmad Atamli , Ilan Pardo , Ariel Shahar , Uria Basher
CPC classification number: G06F21/53 , G06F21/79 , G06F9/5016 , G06F9/5077 , G06F13/28
Abstract: A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.
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