公开(公告)号：US20230245695A1

公开(公告)日：2023-08-03

申请号：US17649885

申请日：2022-02-03

Applicant: Micron Technology, Inc.

Inventor： Tao Jiang ,  Bo Zhou ,  Guang Hu

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4099 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4076 ,  G11C11/4096

Abstract: Methods, systems, and devices for reference voltage adjustment for word line groups are described. In some examples, one or more components of a memory system may determine a duration that data has been stored to one or more memory cells. Based on the duration, a voltage value of one or more reference voltages may be adjusted accordingly. For example, a voltage value of one or more reference voltages may be adjusted based on the duration. Moreover, the reference voltage values may be adjusted differently in response to the memory cells having stored data for a relatively longer duration, as opposed to memory cells that have stored data for a relatively shorter duration. The adjusted reference voltages may be used during a subsequent read operation. The voltage value of the one or more reference voltages may be adjusted on a word-line group by word-line group basis.

公开(公告)号：US20220404968A1

公开(公告)日：2022-12-22

申请号：US17726255

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Bo Zhou ,  Qilin Pan

IPC: G06F3/06 ,  G06F1/28

Abstract: Methods, systems, and devices for read performance techniques for time retention are described. A memory system may store data in a block of memory cells and perform a power cycle operation. Based on performing the power cycle operation, the memory system may determine a first voltage offset associated with the block of memory cells by executing a first read command using an auto-read calibration operation. Based on the first voltage offset, and, in some examples, one or more additional voltage offsets, the memory system may calculate a retention time of data stored in the block of memory cells. The memory system may adjust a read voltage based on the retention time and perform one or more additional read commands.

公开(公告)号：US20210391013A1

公开(公告)日：2021-12-16

申请号：US17458211

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Jingxun Eric Wu ,  Yingying Zhu ,  Hui Yang ,  Bo Zhou

IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06 ,  G11C16/26 ,  G11C16/06 ,  G11C29/10 ,  G11C29/50

Abstract: A memory device comprises a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.