公开(公告)号：US20220291860A1

公开(公告)日：2022-09-15

申请号：US17196584

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： David Matthew Springberg

IPC: G06F3/06

Abstract: Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.

公开(公告)号：US20190361613A1

公开(公告)日：2019-11-28

申请号：US15990497

申请日：2018-05-25

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley ,  David Matthew Springberg ,  Dustin James Carter

IPC: G06F3/06 ,  G06F13/42

Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

公开(公告)号：US12222805B2

公开(公告)日：2025-02-11

申请号：US18110684

申请日：2023-02-16

Applicant: Micron Technology, Inc.

Inventor： David Matthew Springberg

IPC: G06F11/10 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.

公开(公告)号：US20240319912A1

公开(公告)日：2024-09-26

申请号：US18733495

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： David Matthew Springberg

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0679

Abstract: Various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., SGL) provided by a host system for the read operation.

公开(公告)号：US11599414B2

公开(公告)日：2023-03-07

申请号：US17216087

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： David Matthew Springberg

IPC: G06F11/10 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.

公开(公告)号：US11474705B2

公开(公告)日：2022-10-18

申请号：US16932116

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Matthew David Rowley ,  David Matthew Springberg ,  Dustin James Carter

IPC: G06F3/06 ,  G06F13/42

Abstract: Disclosed is a power management integrated circuit with embedded address resolution protocol functionality. In one embodiment, a device is disclosed comprising a data storage device; and an address resolution protocol (ARP) state machine communicatively coupled to the data storage device and included within a power management integrated circuit (PMIC), the ARP state machine configured to assign an address to the data storage device and validate requests for data stored in the data storage device received over a bus.

公开(公告)号：US10175902B2

公开(公告)日：2019-01-08

申请号：US15194202

申请日：2016-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Matthew Springberg ,  Matthew David Rowley ,  Peter Edward Kaineg

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device. The SSD also include a regulator configured to receive an instruction to enter a low power mode of the SSD, enter the low power mode upon receipt of the instruction, receive an indication to exit the low power mode, and exit the low power mode upon receipt of the indication.