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公开(公告)号：US20190033905A1
公开(公告)日：2019-01-31
申请号：US16146982
申请日：2018-09-28
Applicant: MICRON TECHNOLOGY, INC.
Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.
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公开(公告)号：US09252709B2
公开(公告)日：2016-02-02
申请号：US13882144
申请日：2012-10-19
Applicant: MICRON TECHNOLOGY, INC.
CPC classification number: H03B5/24 , H03B5/04 , H03B9/141 , H03L1/00 , H03L7/0891
Abstract: Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a capacitance circuit is configured to be charged and discharged. Charging and discharging circuits are coupled to the capacitance circuit and configured to charge and discharge, respectively, the capacitance circuit by charging and discharging currents responsive to charge and discharge signals. A control circuit is coupled to the charging circuit and the discharging circuit, and is configured to provide the charge and discharge signals responsive to a voltage of the capacitance circuit, and is further configured to provide an oscillation signal responsive to the voltage of the capacitance circuit. The charging current, the discharging current, or both the charging and discharging currents are proportional to a difference between a first reference voltage and a second reference voltage.
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公开(公告)号：US20140176249A1
公开(公告)日：2014-06-26
申请号：US13882144
申请日：2012-10-19
Applicant: MICRON TECHNOLOGY, INC
IPC: H03B9/14
CPC classification number: H03B5/24 , H03B5/04 , H03B9/141 , H03L1/00 , H03L7/0891
Abstract: Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a capacitance circuit is configured to be charged and discharged. Charging and discharging circuits are coupled to the capacitance circuit and configured to charge and discharge, respectively, the capacitance circuit by charging and discharging currents responsive to charge and discharge signals. A control circuit is coupled to the charging circuit and the discharging circuit, and is configured to provide the charge and discharge signals responsive to a voltage of the capacitance circuit, and is further configured to provide an oscillation signal responsive to the voltage of the capacitance circuit. The charging current, the discharging current, or both the charging and discharging currents are proportional to a difference between a first reference voltage and a second reference voltage.
Abstract translation: 公开了对电源电压变化基本上不敏感的振荡器的装置和方法。 在一个这样的示例性装置中，电容电路被配置为被充电和放电。 充电和放电电路耦合到电容电路并且被配置为通过响应于充电和放电信号的充电和放电电流对电容电路进行充电和放电。 控制电路耦合到充电电路和放电电路，并且被配置为响应于电容电路的电压来提供充电和放电信号，并且还被配置为提供响应于电容电路的电压的振荡信号 。 充电电流，放电电流或充电和放电电流都与第一参考电压和第二参考电压之间的差成比例。
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14.发明申请公开(公告)号：US20210335411A1
公开(公告)日：2021-10-28
申请号：US17324621
申请日：2021-05-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406
Abstract: Apparatuses and methods for pure-time, self-adopt sampling for RHR refresh. An example apparatus includes a memory bank comprising a plurality of rows each associated with a respective row address, and a sampling timing generator circuit configured to provide a timing signal having a plurality of pulses. Each of the plurality of pulses is configured to initiate sampling of a respective row address associated with a row of the plurality of rows to detect a row hammer attack. The sampling timing generator includes first circuitry configured to provide a first subset of pulses of the plurality of pulses during a first time period and includes second circuitry configured to initiate provision of a second subset of pulses of the plurality of pulses during a second time period after the first time period.
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公开(公告)号：US20210158860A1
公开(公告)日：2021-05-27
申请号：US17168036
申请日：2021-02-04
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.
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Patent Agency Ranking
公开(公告)号：US20210057021A1
公开(公告)日：2021-02-25
申请号：US16546152
申请日：2019-08-20
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access hacking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.
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公开(公告)号：US10824550B2
公开(公告)日：2020-11-03
申请号：US16540654
申请日：2019-08-14
Applicant: Micron Technology, Inc.
IPC: G06F12/00 , G11C15/04 , H03K19/1776 , H03K19/20 , G11C11/408 , G11C11/406 , G06F13/00 , G06F13/28
Abstract: A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval.
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公开(公告)号：US20200090750A1
公开(公告)日：2020-03-19
申请号：US16540654
申请日：2019-08-14
Applicant: Micron Technology, Inc.
IPC: G11C15/04 , H03K19/177 , H03K19/20
Abstract: A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval.
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公开(公告)号：US10572377B1
公开(公告)日：2020-02-25
申请号：US16135877
申请日：2018-09-19
Applicant: Micron Technology, Inc.
IPC: G06F12/00 , G06F13/00 , G11C15/04 , H03K19/1776 , H03K19/20 , G11C11/408 , G11C11/406 , G06F13/28
Abstract: A method of operating a memory device may include receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM). The method may further include storing, during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Moreover, the method may include refreshing each stored RHA of the CAM via a RHR during the RHR interval. Semiconductor devices and an electronic system are also described.
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公开(公告)号：US10277427B1
公开(公告)日：2019-04-30
申请号：US15871636
申请日：2018-01-15
Applicant: Micron Technology, Inc.
Abstract: A device includes a first terminal configured to receive a reference voltage, a second terminal configured to receive a weighted tap value, a local generator circuit configured to create a group of unsigned voltage correction values based on the reference voltage and the weighted tap value, and a sign configuring circuit configured to receive the group of unsigned voltage correction values from the local generator circuit and assign a polarity to each respective unsigned voltage correction value of the group of unsigned voltage correction values, creating correction signals from the group of unsigned voltage correction values. The device also includes an output configured to transmit the correction signals to a first input of a processing circuit, wherein the processing circuit is configured to use the correction signals to offset inter-symbol interference from a data stream on a distorted bit based at least on a control signal.
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