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公开(公告)号：US11605442B2
公开(公告)日：2023-03-14
申请号：US17483009
申请日：2021-09-23
Applicant: MICRON TECHNOLOGY, INC.
Abstract: Embodiments of the disclosure are drawn to apparatuses methods for checking redundancy information for row addresses prior to performing various refresh operations, such as auto refresh and targeted refresh operations. In some examples, refresh operations may be multi pump refresh operations. In some examples, a targeted refresh operation may be performed prior to an auto refresh operation responsive to a multi pump refresh operation. In some examples, redundancy information for the auto refresh operation may be performed, at least in part, during the targeted refresh operation. In some examples, refresh operations on word lines may be skipped when the redundancy information indicates the word line is defective or unused.
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公开(公告)号：US20220189539A1
公开(公告)日：2022-06-16
申请号：US17654035
申请日：2022-03-08
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C29/20
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic targeted refresh steals. A memory bank ma receive access commands and then periodically enter a refresh mode, where auto refresh operations and targeted refresh operations are performed. The memory bank may receive a refresh management command based on a count of access commands directed to the memory bank. Responsive to the refresh management signal, a panic targeted refresh operation may be performed on the memory bank. A number of times the refresh management signal was issued may be counted, and based on that count a next periodic targeted refresh operation may be skipped.
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公开(公告)号：US20210158860A1
公开(公告)日：2021-05-27
申请号：US17168036
申请日：2021-02-04
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access tracking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.
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公开(公告)号：US20210057021A1
公开(公告)日：2021-02-25
申请号：US16546152
申请日：2019-08-20
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for analog row access hacking. A plurality of unit cells are provided, each of which contains one or more analog circuits used to track accesses to a portion of the wordlines of a memory device. When a wordline in the portion is accessed, the unit cell may update an accumulator voltage, for example by adding charge to a capacitor. A comparator circuit may determine when one or more accumulator voltages cross a threshold (e.g., a reference voltage). Responsive to the accumulator voltage crossing the threshold, an aggressor address may be loaded in a targeted refresh queue, or if the aggressor address is already in the queue, a priority flag associated with that address may be set. Aggressor addresses may be provided to have their victims refreshed in an order based on the number of set priority flags.
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公开(公告)号：US10824550B2
公开(公告)日：2020-11-03
申请号：US16540654
申请日：2019-08-14
Applicant: Micron Technology, Inc.
IPC: G06F12/00 , G11C15/04 , H03K19/1776 , H03K19/20 , G11C11/408 , G11C11/406 , G06F13/00 , G06F13/28
Abstract: A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval.
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Patent Agency Ranking
公开(公告)号：US20200090750A1
公开(公告)日：2020-03-19
申请号：US16540654
申请日：2019-08-14
Applicant: Micron Technology, Inc.
IPC: G11C15/04 , H03K19/177 , H03K19/20
Abstract: A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval.
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公开(公告)号：US10572377B1
公开(公告)日：2020-02-25
申请号：US16135877
申请日：2018-09-19
Applicant: Micron Technology, Inc.
IPC: G06F12/00 , G06F13/00 , G11C15/04 , H03K19/1776 , H03K19/20 , G11C11/408 , G11C11/406 , G06F13/28
Abstract: A method of operating a memory device may include receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM). The method may further include storing, during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Moreover, the method may include refreshing each stored RHA of the CAM via a RHR during the RHR interval. Semiconductor devices and an electronic system are also described.
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公开(公告)号：US20200036396A1
公开(公告)日：2020-01-30
申请号：US16593479
申请日：2019-10-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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公开(公告)号：US20220270670A1
公开(公告)日：2022-08-25
申请号：US17662733
申请日：2022-05-10
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/4096 , G11C11/4091 , G11C11/408 , G11C11/402
Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.
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公开(公告)号：US11380382B2
公开(公告)日：2022-07-05
申请号：US16997766
申请日：2020-08-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for providing refresh logic, such as row hammer refresh circuitry, in a location on a memory die apart from a bank logic region of the memory die. In some examples, at least some of the components of the row hammer refresh circuitry may be shared between banks of the memory.
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