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公开(公告)号：US20220059158A1
公开(公告)日：2022-02-24
申请号：US16997659
申请日：2020-08-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/406 , G11C11/408 , G11C11/4091 , G11C11/4096
Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.
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公开(公告)号：US20190229955A1
公开(公告)日：2019-07-25
申请号：US16375510
申请日：2019-04-04
Applicant: Micron Technology, Inc.
Abstract: A device includes a first terminal configured to receive a reference voltage, a second terminal configured to receive a weighted tap value, a local generator circuit configured to create a group of unsigned voltage correction values based on the reference voltage and the weighted tap value, and a sign configuring circuit configured to receive the group of unsigned voltage correction values from the local generator circuit and assign a polarity to each respective unsigned voltage correction value of the group of unsigned voltage correction values, creating correction signals from the group of unsigned voltage correction values. The device also includes an output configured to transmit the correction signals to a first input of a processing circuit, wherein the processing circuit is configured to use the correction signals to offset inter-symbol interference from a data stream on a distorted bit based at least on a control signal.
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公开(公告)号：US20170177019A1
公开(公告)日：2017-06-22
申请号：US15117681
申请日：2016-06-06
Applicant: Micron Technology, Inc.
IPC: G05F3/26
CPC classification number: G05F3/26
Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.
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公开(公告)号：US11749331B2
公开(公告)日：2023-09-05
申请号：US17662733
申请日：2022-05-10
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/4091 , G11C11/408 , G11C11/402
CPC classification number: G11C11/40611 , G11C11/402 , G11C11/4085 , G11C11/4091 , G11C11/4096 , G11C11/40603 , G11C11/40618
Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.
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公开(公告)号：US20220317975A1
公开(公告)日：2022-10-06
申请号：US17217861
申请日：2021-03-30
Applicant: Micron Technology, Inc.
IPC: G06F7/58
Abstract: Linear-feedback shift registers (LFSRs) for generating bounded random numbers (e.g., random numbers within a narrower range than those generated by a conventional LFSR of the same width) are described. In one embodiment, a bounded LFSR for generating an n-bit value comprises an m-bit LFSR with a range of 2m random numbers and an n−m bit LFSR with a range of 2n−m−1−k random numbers. The bounded LFSR further comprises logic to skip k values from a repeatable sequence of the n−m bit LFSR, which can, for example, be configured during the design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on the outputs of the m-bit LFSR and the n−m bit LFSR. In one embodiment, the bounded random number generated by the bounded LFSR is used as a random address in a row hammer mitigation system.
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Patent Agency Ranking
公开(公告)号：US11348631B2
公开(公告)日：2022-05-31
申请号：US16997659
申请日：2020-08-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C11/402 , G11C11/406 , G11C11/4096 , G11C11/4091 , G11C11/408
Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.
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公开(公告)号：US11150681B2
公开(公告)日：2021-10-19
申请号：US16203215
申请日：2018-11-28
Applicant: Micron Technology, Inc.
Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.
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8.发明授权公开(公告)号：US11017833B2
公开(公告)日：2021-05-25
申请号：US16084119
申请日：2018-05-24
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C7/00 , G11C11/406
Abstract: Apparatuses and methods for pure-time, self-adopt sampling for RHR refresh. An example apparatus includes a memory bank comprising a plurality of rows each associated with a respective row address, and a sampling timing generator circuit configured to provide a timing signal having a plurality of pulses. Each of the plurality of pulses is configured to initiate sampling of a respective row address associated with a row of the plurality of rows to detect a row hammer attack. The sampling timing generator includes first circuitry configured to provide a first subset of pulses of the plurality of pulses during a first time period and includes second circuitry configured to initiate provision of a second subset of pulses of the plurality of pulses during a second time period after the first time period.
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公开(公告)号：US10860470B2
公开(公告)日：2020-12-08
申请号：US16540654
申请日：2019-08-14
Applicant: Micron Technology, Inc.
IPC: G06F12/00 , G11C15/04 , H03K19/1776 , H03K19/20 , G11C11/408 , G11C11/406 , G06F13/00 , G06F13/28
Abstract: A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval.
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公开(公告)号：US20200273502A1
公开(公告)日：2020-08-27
申请号：US16646503
申请日：2017-09-22
Applicant: Micron Technology, Inc.
IPC: G11C5/14 , G11C16/30 , G11C11/4074
Abstract: Apparatus and methods that have a semiconductor charge pump can be implemented in a variety of applications. Such a charge pump can have a charge pump unit core that includes a pump section and a single passgate coupled to the pump section to transfer charge, where the single passgate is a n-channel metal-oxide semiconductor (NMOS) transistor coupled directly to an input and an output of the charge pump unit core. The transfer of charge can be based on a set of clock signals. Additional apparatus, systems, and methods are disclosed.
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