公开(公告)号：US11061836B2

公开(公告)日：2021-07-13

申请号：US16448188

申请日：2019-06-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/08 ,  G06F13/16 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage between a data input node and a data output node. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The clock path includes a plurality of clock stages corresponding to the plurality of wave pipeline data stages between an input clock node and a return clock node. Each clock stage has a delay configured to be equal to a delay of the corresponding wave pipeline data stage. The wave pipeline includes a second data latch to latch the data on the data output node in response to a return clock signal on the return clock node. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

公开(公告)号：US20210110856A1

公开(公告)日：2021-04-15

申请号：US17247267

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C7/10 ,  G11C8/18

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

公开(公告)号：US10891993B2

公开(公告)日：2021-01-12

申请号：US16429209

申请日：2019-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.