公开(公告)号：US20190295614A1

公开(公告)日：2019-09-26

申请号：US16429209

申请日：2019-06-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/18 ,  G11C8/04 ,  G11C7/10

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US20190180802A1

公开(公告)日：2019-06-13

申请号：US15834315

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/04 ,  G11C8/06 ,  G11C8/18 ,  G11C16/0483

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

公开(公告)号：US20190355400A1

公开(公告)日：2019-11-21

申请号：US16531244

申请日：2019-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G11C16/04 ,  G11C8/06

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

公开(公告)号：US10360956B2

公开(公告)日：2019-07-23

申请号：US15834279

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C8/18 ,  G11C16/04

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US20190180801A1

公开(公告)日：2019-06-13

申请号：US15834279

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/18 ,  G11C8/04 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C8/04 ,  G11C8/06 ,  G11C8/18 ,  G11C16/0483

Abstract: A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

公开(公告)号：US11367473B2

公开(公告)日：2022-06-21

申请号：US17247267

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam ,  Qiang Tang ,  Eric N. Lee

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/06 ,  G11C8/06 ,  G11C8/04 ,  G11C7/10 ,  G11C8/18 ,  G11C16/04

Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.

公开(公告)号：US11544208B2

公开(公告)日：2023-01-03

申请号：US17324172

申请日：2021-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G06F1/08 ,  G06F13/16 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.

公开(公告)号：US10714160B2

公开(公告)日：2020-07-14

申请号：US16531244

申请日：2019-08-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C7/10 ,  G11C16/04 ,  G11C8/18 ,  G11C8/06 ,  G11C8/04

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

公开(公告)号：US10410698B2

公开(公告)日：2019-09-10

申请号：US15834315

申请日：2017-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/04 ,  G11C8/18 ,  G11C8/06 ,  G11C16/04

Abstract: A wave pipeline includes a plurality of data paths, a clock signal path, and a return clock signal path. Each data path includes an input node, an output node, and a data stage between the input node and the output node. Each data path has a different delay between the input node and the output node. A first data path of the plurality of data paths has a first delay and each of the other data paths of the plurality of data paths have a delay less than the first delay. The clock signal path provides a clock signal to the data stage of each data path. The return clock signal path provides a return clock signal from the data stage of the first data path. The return clock signal triggers data out of the data stage of each data path of the plurality of data paths.

公开(公告)号：US20210271618A1

公开(公告)日：2021-09-02

申请号：US17324172

申请日：2021-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kaveh Shakeri ,  Ali Feiz Zarrin Ghalam

IPC: G06F13/16 ,  G11C16/08 ,  G11C16/32 ,  G11C16/04

Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.