公开(公告)号：US20240136015A1

公开(公告)日：2024-04-25

申请号：US18049498

申请日：2022-10-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G06F16/903

CPC classification number: G16B30/10 ,  G06F16/90339

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US20190042100A1

公开(公告)日：2019-02-07

申请号：US16132099

申请日：2018-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Sean E. Eilert

IPC: G06F3/06

Abstract: Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory system is configured to receive instructions from the processor to access information stored by the memory system. The memory system includes a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled to at least one other memory node of the plurality of memory nodes, and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation, the internal message to be provided to another memory node of the plurality of memory nodes to perform the operation.

公开(公告)号：US20250124981A1

公开(公告)日：2025-04-17

申请号：US18999983

申请日：2024-12-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G11C13/00 ,  C12Q1/6869 ,  G11C7/16 ,  G16B30/10

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US12217796B2

公开(公告)日：2025-02-04

申请号：US17931277

申请日：2022-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G11C13/00 ,  C12Q1/6869 ,  G11C7/16 ,  G16B30/10

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US20240136016A1

公开(公告)日：2024-04-25

申请号：US18049506

申请日：2022-10-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G16B50/00

CPC classification number: G16B30/10 ,  G16B50/00

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US11899961B2

公开(公告)日：2024-02-13

申请号：US17652229

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US10761781B2

公开(公告)日：2020-09-01

申请号：US16132099

申请日：2018-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Sean E. Eilert

IPC: G06F12/00 ,  G06F3/06

Abstract: Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory system is configured to receive instructions from the processor to access information stored by the memory system. The memory system includes a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled to at least one other memory node of the plurality of memory nodes, and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation, the internal message to be provided to another memory node of the plurality of memory nodes to perform the operation.

公开(公告)号：US10089043B2

公开(公告)日：2018-10-02

申请号：US13842984

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Sean S. Eilert

IPC: G06F12/00 ,  G06F3/06

Abstract: Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory system is configured to receive instructions from the processor to access information stored by the memory system. The memory system includes a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled to at least one other memory node of the plurality of memory nodes, and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation, the internal message to be provided to another memory node of the plurality of memory nodes to perform the operation.

公开(公告)号：US20250087294A1

公开(公告)日：2025-03-13

申请号：US18775881

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Sukneet S. Basuta ,  Kenneth M. Curewitz

IPC: G11C29/00

Abstract: Memory devices can be protected (e.g., repaired) against hard bit errors by remapping logical pages to valid physical addresses and excluding those physical addresses having hard bit errors from being mapped to. The remapping can be done in unit of a finer granularity than a row of memory cells such that those valid memory cells within a row can still be used for the remapping despite that the row may include unusable memory cells.

公开(公告)号：US20240369632A1

公开(公告)日：2024-11-07

申请号：US18772690

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Kenneth M. Curewitz ,  Jaime Cummins ,  John D. Porter ,  Bryce D. Cook ,  Jeffrey P. Wright

IPC: G01R31/319 ,  G01R31/3185

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.