公开(公告)号：US20250165762A1

公开(公告)日：2025-05-22

申请号：US19019737

申请日：2025-01-14

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06N3/049 ,  G06N3/084 ,  G06N5/046 ,  G11C11/4063 ,  G11C11/54

Abstract: Systems and methods are disclosed. A system may include a number of memory arrays and circuitry coupled to the number of memory arrays. The circuitry may store synaptic connections of a destination neuron in a first memory array of the number of memory arrays. The circuitry may also store pre-synaptic spike events from respective source neurons in a second memory array of the number of memory arrays. In response to a match of a neuron identification of the synaptic connections of the destination neuron with a neuron identification of the source neurons, the circuitry may generate a signal. The circuitry may further drive, based on the signal, at least one word line of a third memory array of the number of memory arrays.

公开(公告)号：US20250124981A1

公开(公告)日：2025-04-17

申请号：US18999983

申请日：2024-12-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G11C13/00 ,  C12Q1/6869 ,  G11C7/16 ,  G16B30/10

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US12217796B2

公开(公告)日：2025-02-04

申请号：US17931277

申请日：2022-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G11C13/00 ,  C12Q1/6869 ,  G11C7/16 ,  G16B30/10

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US20240404581A1

公开(公告)日：2024-12-05

申请号：US18667791

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Brent Keeth ,  James Brian Johnson ,  Chun-Yi Liu ,  Shivasankar Gunasekaran ,  Paul A. Laberge ,  Gregory A. King ,  Sai Krishna Mylavarapu ,  Su Wei Lim ,  Nathan A. Eckel ,  Lance P. Johnson ,  Nathan D. Henningson

IPC: G11C11/4093 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Methods, systems, and devices for interface techniques for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute memory access circuitry among multiple semiconductor dies of a stack. A first die of the system may include logic circuitry operable to configure a set of multiple first interface blocks of the first die. Each first interface block may include circuitry operable to communicate with one or more second interface blocks of one or more second dies of the system to access a respective set of one or more memory arrays of the one or more second dies. In some examples, the system may include a respective controller for each first interface block to support access operations via the first interface block. The system may also include non-volatile storage, one or more sensors, or a combination thereof to support various operations of the system.

公开(公告)号：US20240345957A1

公开(公告)日：2024-10-17

申请号：US18751020

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/0837 ,  G06F9/38 ,  G06F11/14 ,  G06F12/1009 ,  G06F12/1027 ,  G06N3/02

CPC classification number: G06F12/0837 ,  G06F9/3877 ,  G06F11/1448 ,  G06F12/1009 ,  G06F12/1027 ,  G06N3/02

Abstract: Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.

公开(公告)号：US20240281167A1

公开(公告)日：2024-08-22

申请号：US18649465

申请日：2024-04-29

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Justin Eno ,  Brian Hirano

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

公开(公告)号：US20240176523A1

公开(公告)日：2024-05-30

申请号：US18516734

申请日：2023-11-21

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin ,  Ameen D. Akel

IPC: G06F3/06 ,  G06F1/06

CPC classification number: G06F3/064 ,  G06F1/06 ,  G06F3/061 ,  G06F3/0683

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of the circuitry configured to access the set of memory arrays, and a second die may include a second portion of the circuitry configured to access the set of memory arrays. The first portion and the second portion of the circuitry configured to access a set of memory arrays may be communicatively coupled between the dies using various interconnection techniques, such as a fusion of conductive contacts of the respective memory dies. In some examples, the second die may also include the host itself (e.g., a host processor).

公开(公告)号：US20240136016A1

公开(公告)日：2024-04-25

申请号：US18049506

申请日：2022-10-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G16B50/00

CPC classification number: G16B30/10 ,  G16B50/00

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US11954042B2

公开(公告)日：2024-04-09

申请号：US17943739

申请日：2022-09-13

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L67/1097 ,  H04W84/04

CPC classification number: G06F12/10 ,  H04L67/1097 ,  G06F2212/154 ,  G06F2212/657 ,  H04W84/042

Abstract: Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US11899961B2

公开(公告)日：2024-02-13

申请号：US17652229

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.