公开(公告)号：US12165688B2

公开(公告)日：2024-12-10

申请号：US17747183

申请日：2022-05-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yankang He ,  Walter Di Francesco ,  Luca Nubile ,  Chang Siau

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4094

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

公开(公告)号：US20240272812A1

公开(公告)日：2024-08-15

申请号：US18621747

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

公开(公告)号：US20240241643A1

公开(公告)日：2024-07-18

申请号：US18407239

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Biagio Iorio ,  Luca Nubile ,  Walter Di Francesco ,  Jeremy Binfet ,  Liang Yu ,  Yankang He ,  Ali Mohammadzadeh

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic on a memory die of a multi-die memory sub-system receives, from a memory sub-system controller, a data burst command indicating an upcoming data burst event and determines an expected current utilization in the memory sub-system during the data burst event. The control logic further determines whether the expected current utilization in the memory sub-system during the data burst event satisfies a threshold criterion and responsive to determining that the expected current utilization in the memory sub-system during the data burst event does not satisfy the threshold criterion, pauses one or more operations being executed by the control logic on the memory die until the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion. Responsive to determining that the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion, the control logic provides, to the memory sub-system controller, an indication that the data burst event is approved and can perform one or more operations corresponding to the data burst event.

公开(公告)号：US11977748B2

公开(公告)日：2024-05-07

申请号：US17668311

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

公开(公告)号：US20230084630A1

公开(公告)日：2023-03-16

申请号：US17668311

申请日：2022-02-09

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.