公开(公告)号：US11342906B2

公开(公告)日：2022-05-24

申请号：US17201294

申请日：2021-03-15

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Zhi Qi Huang

IPC: G11C7/00 ,  H03K5/134 ,  G11C11/408 ,  H03K5/131

Abstract: Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.

公开(公告)号：US20220157365A1

公开(公告)日：2022-05-19

申请号：US16952804

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C11/4076 ,  G11C11/22

Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.

公开(公告)号：US20220076720A1

公开(公告)日：2022-03-10

申请号：US17526846

申请日：2021-11-15

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C7/22 ,  G11C7/04 ,  G11C7/10

Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.

公开(公告)号：US20210203316A1

公开(公告)日：2021-07-01

申请号：US17201294

申请日：2021-03-15

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Zhi Qi Huang

IPC: H03K5/134 ,  G11C11/408 ,  H03K5/131

Abstract: Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed.

公开(公告)号：US10998893B2

公开(公告)日：2021-05-04

申请号：US16085870

申请日：2018-08-01

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Zhi Qi Huang

IPC: G11C7/00 ,  H03K5/134 ,  G11C11/408 ,  H03K5/131

Abstract: Methods and apparatus for generating a delayed output signal from an input signal applied to an RC delay circuit of a semiconductor device during an active mode. The RC delay circuit is configured to pull up a voltage level on a node responsive to a reset signal during a stand-by mode.

公开(公告)号：US20240386941A1

公开(公告)日：2024-11-21

申请号：US18425149

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Dong Pan ,  Scott D. Van De Graaff

IPC: G11C11/4093 ,  G11C29/50 ,  G11C11/4076

Abstract: Systems and methods described herein may increase voltages sensed during testing of a device-under-test, which may increase an ease of sensing by a comparator, where a relatively less sensitive comparator may be used to detect the increased voltage sensed. Indeed, first readout circuitry may include two or more diodes coupled in series to a first resistor, which may help increase the voltages sensed via the first readout circuitry.

公开(公告)号：US11804255B2

公开(公告)日：2023-10-31

申请号：US17393597

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu

IPC: G11C11/4074 ,  G05F3/26 ,  H03F3/45

CPC classification number: G11C11/4074 ,  G05F3/262 ,  H03F3/45269 ,  H03F3/45273

Abstract: A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.

公开(公告)号：US11335396B1

公开(公告)日：2022-05-17

申请号：US16952804

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/22

Abstract: Methods, systems, and devices for timing signal delay for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. A memory device may include delay components having a configurable impedance based at least in part on one or more fabrication characteristics of the memory device, one or more operating conditions of the memory device, one or more bias voltages, or a combination thereof.

公开(公告)号：US11227650B1

公开(公告)日：2022-01-18

申请号：US17002398

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C8/18 ,  G11C11/4076

Abstract: An electronic device includes a first input that receives an input signal when the electronic device is in operation, a long L gate comprising a long L transistor, a first activation transistor coupled to a gate of the long L transistor, and a second activation transistor coupled to the gate of the long L transistor. The electronic device also includes a switch directly coupled to a second input of the long L gate, a path directly coupled to a first output of the long L gate, a capacitor coupled to the path, and a second output that when in operation transmits an output signal as a delayed signal with respect to the input signal.

公开(公告)号：US11200927B2

公开(公告)日：2021-12-14

申请号：US16843628

申请日：2020-04-08

Applicant: Micron Technology, Inc.

Inventor： Zhi Qi Huang ,  Wei Lu Chu ,  Dong Pan

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/04 ,  G11C7/10

Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.