公开(公告)号：US5172047A

公开(公告)日：1992-12-15

申请号：US644634

申请日：1991-01-23

申请人： Teruhiko Funakura

发明人： Teruhiko Funakura

IPC分类号： G01R31/28 ,  G01R31/26 ,  G01R31/3193

CPC分类号： G01R31/2601 ,  G01R31/3193

摘要： A semiconductor test apparatus for testing the characteristics of a semiconductor device having a plurality of output pins includes a plurality of level determination devices, arranged in correspondence with respective output pins of the semiconductor device, for determining the output levels from corresponding output pins, a data preparation device for preparing combination data by selectively combining the outputs of the plurality of level determination devices, a retaining device for retaining combination data prepared by the data preparation device, at least two storage devices, each for storing set values, at least two comparison devices, arranged in correspondence with respective storage devices, each for comparing combination data retained in the retaining device with the set values stored in the corresponding storage devices, and a determination device for determining the characteristics of the semiconductor devices from the comparison results of the comparison devices.

摘要翻译： 用于测试具有多个输出引脚的半导体器件的特性的半导体测试装置包括：与半导体器件的相应输出引脚对应地布置的多个电平确定器件，用于确定来自相应输出引脚的输出电平，数据 用于通过选择性地组合多个级别确定装置的输出来准备组合数据的准备装置，用于保存由数据准备装置准备的组合数据的保持装置，用于存储设定值的至少两个存储装置，至少两个比较装置 与各个存储装置相对应地布置，用于将保留装置中保留的组合数据与存储在相应的存储装置中的设定值进行比较;以及确定装置，用于根据比较装置的比较结果确定半导体装置的特性 。

公开(公告)号：US06653855B2

公开(公告)日：2003-11-25

申请号：US09927366

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G01R3102

CPC分类号： G01R31/319

摘要： A BOST (built-off self-test) board has a connector, a substrate for use with a BOST board, and an external self-test circuit. The external self-test circuit has an ADC (analog-to-digital converter)/DAC (digital-to-analog converter) measurement section and a DSP (digital signal processor). In accordance with a control signal input by way of a specific terminal provided in a connector, the ADC/DAC measurement section transmits a predetermined test signal to the specific terminal provided in the connector. Further, in response to the test signal, the ADC/DAC measurement section receives a response signal input to the specific terminal provided in the connector. The DSP analysis section analyzes the response signal, thereby determining whether or not the response signal is an appropriate signal. Further, the DSP analysis section transmits, to the specific terminal provided in the connector, a test result signal indicating whether or not the response signal is appropriate.

公开(公告)号：US06628137B2

公开(公告)日：2003-09-30

申请号：US09927471

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G01R3126

CPC分类号： G01R31/31926

摘要： There are provided a test apparatus and a test method for testing a semiconductor integrated circuit which facilitate control of a BOST device and improve the versatility of the BOST device. There is provided an interface for exchanging signals between a BOST device and an external controller. A test control signal and a test result analysis signal are exchanged by means of the interface, thus effecting a test and analysis of the test.

公开(公告)号：US06522126B1

公开(公告)日：2003-02-18

申请号：US09684779

申请日：2000-10-10

申请人： Hisayoshi Hanai ,  Teruhiko Funakura ,  Yasuhiro Mabuchi

发明人： Hisayoshi Hanai ,  Teruhiko Funakura ,  Yasuhiro Mabuchi

IPC分类号： G01R3126

CPC分类号： G01R31/31922

摘要： A low-cost semiconductor tester which saves memory space for storing a test pattern by means of producing a high-speed clock while preparing a test pattern at a low-speed test cycle and which has a test-pattern storage circuit of small storage capacity, as well as a semiconductor test method using the semiconductor tester. The semiconductor tester includes a reference-signal-generation circuit for producing a test cycle to be taken as a reference-signal, a waveform formation circuit for producing the geometry of an output waveform on the basis of the test cycle, and a waveform output circuit which sets the voltage of the geometry of the output waveform and applies the voltage to a semiconductor element to be measured. A ring oscillation circuit is provided in the waveform formation circuit and has a variable delay circuit. The ring oscillation circuit converts the output waveform, which waveform is produced at a predetermined timing, into a high-speed clock waveform.

摘要翻译： 一种低成本的半导体测试器，其通过在低速测试周期准备测试图案的同时产生高速时钟来节省用于存储测试图案的存储空间，并且具有小存储容量的测试图案存储电路， 以及使用半导体测试器的半导体测试方法。 半导体测试器包括用于产生要作为参考信号的测试周期的参考信号产生电路，用于产生基于测试周期的输出波形的几何形状的波形形成电路和波形输出电路 其设置输出波形的几何形状的电压并将电压施加到待测量的半导体元件。 环形振荡电路设置在波形形成电路中并具有可变延迟电路。 环形振荡电路将在预定定时产生的波形的输出波形转换为高速时钟波形。

公开(公告)号：US06990614B1

公开(公告)日：2006-01-24

申请号：US09641352

申请日：2000-08-18

申请人： Hidekazau Nagasawa ,  Teruhiko Funakura ,  Kazushi Sugiura ,  Hisaya Mori

发明人： Hidekazau Nagasawa ,  Teruhiko Funakura ,  Kazushi Sugiura ,  Hisaya Mori

IPC分类号： G06F11/00

CPC分类号： G11C16/24 ,  G11C2029/1806 ,  G11C2029/5602 ,  G11C2029/5606

摘要： A data storage apparatus comprising a scrambling circuit 34 for converting address signals and error data output by a tester 24 to a desired format, and a storage device 28 for storing the converted data. The scrambling circuit 34 includes a plurality of conversion circuits 40, 42 and 44 each converting the signals from the tester 24 according to different rules, and a selector 46 for selecting one of signals output by the conversion circuits 40, 42 and 44 and for supplying what is selected to the storage device.

摘要翻译： 一种数据存储装置，包括用于将地址信号和由测试器24输出的误差数据转换为期望格式的加扰电路34，以及用于存储转换后的数据的存储装置28。 加扰电路34包括多个转换电路40,42和44，每个转换电路根据不同的规则转换来自测试器24的信号;以及选择器46，用于选择由转换电路40,42和44输出的信号之一， 什么是选择到存储设备。

公开(公告)号：US06900627B2

公开(公告)日：2005-05-31

申请号：US09927368

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G01R1/067 ,  G01R31/316 ,  G01R31/3167 ,  G01R31/3183 ,  G01R31/319 ,  H01L21/66 ,  H03M1/10 ,  G01R1/04 ,  G01R31/02

CPC分类号： G01R31/3167

摘要： A test ancillary device with data memory and an analysis section is disposed in the vicinity of a test circuit board. The data memory is divided into two memory sections such that, when digital test data are stored in one memory section, the digital test data that have already been stored in the other memory section are loaded for analysis purpose.

摘要翻译： 具有数据存储器和分析部件的测试辅助装置设置在测试电路板附近。 数据存储器被分成两个存储器部分，使得当数字测试数据存储在一个存储器部分中时，已经存储在另一个存储器部分中的数字测试数据被加载用于分析目的。

公开(公告)号：US5959463A

公开(公告)日：1999-09-28

申请号：US939701

申请日：1997-09-29

申请人： Teruhiko Funakura ,  Kazuya Fujita

发明人： Teruhiko Funakura ,  Kazuya Fujita

IPC分类号： G01R31/26 ,  G01R19/00 ,  G01R31/30

CPC分类号： G01R31/3004

摘要： A power supply voltage (Vcc) is applied to a dummy capacitor having a capacitance identical to that of a bypass capacitor to generate an excessive current. The excessive current is subtracted from a current flowing through an IC and the bypass capacitor to obtain a power supply current (Icc) of the IC. The time required for measuring power supply current (Icc) of the IC is reduced since it is not necessary to wait for attenuation of the excessive current of the bypass capacitor.

摘要翻译： 电源电压（Vcc）被施加到具有与旁路电容器的电容相同的电容的虚拟电容器，以产生过大的电流。 从流过IC和旁路电容器的电流中减去过大的电流，以获得IC的电源电流（Icc）。 测量IC的电源电流（Icc）所需的时间减少，因为不需要等待旁路电容器的过电流的衰减。

公开(公告)号：US07058865B2

公开(公告)日：2006-06-06

申请号：US10647267

申请日：2003-08-26

申请人： Hisaya Mori ,  Teruhiko Funakura ,  Hisayoshi Hanai

发明人： Hisaya Mori ,  Teruhiko Funakura ,  Hisayoshi Hanai

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/56 ,  G01R31/31905 ,  G01R31/31919 ,  G01R31/31926 ,  G06F11/263

摘要： An apparatus for testing a semiconductor integrated circuit has a test circuit board and an ancillary test device. The ancillary test device can test a digital circuit. The ancillary test device has test pattern memory, a test pattern signal generator, and a control section for controlling an operation for the test pattern data selected from among the plurality of test pattern data sets stored in the test pattern memory and an operation for writing the selected test pattern data into the test pattern signal generator. The ancillary test device generates a test input pattern signal on the basis of test pattern data written in the test pattern signal generator and determines a test output pattern signal output from the semiconductor integrated circuit on the basis of the test input pattern signal, thereby testing a digital circuit.

摘要翻译： 用于半导体集成电路测试的装置具有测试电路板和辅助测试装置。 辅助测试设备可以测试数字电路。 辅助测试装置具有测试模式存储器，测试模式信号发生器和用于控制从存储在测试模式存储器中的多个测试模式数据集中选择的测试模式数据的操作的控制部分，以及用于写入 将测试图案数据选入测试图形信号发生器。 辅助测试装置根据写在测试图形信号发生器中的测试图案数据产生测试输入模式信号，并且基于测试输入模式信号确定从半导体集成电路输出的测试输出模式信号，从而测试 数字电路。

公开(公告)号：US06714888B2

公开(公告)日：2004-03-30

申请号：US09927470

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G01R3100

CPC分类号： G01R19/2509 ,  G01R31/319 ,  G01R31/31926 ,  H03M1/1071

摘要： There is provided an apparatus and method of testing a semiconductor integrated circuit, which apparatus and method enable testing of various semiconductor integrated circuits having different characteristics, fulfillment of the function of generating DAC data, and adaptation of various analog characteristic tests. An input range of a BOST device is switchable in accordance with the level of a DAC of a DUT, so that the test apparatus can handle DUTs of different types having different analog output levels.

摘要翻译： 提供了一种测试半导体集成电路的装置和方法，该装置和方法能够测试具有不同特性的各种半导体集成电路，实现产生DAC数据的功能，以及适应各种模拟特性测试。 BOST器件的输入范围可以根据DUT的DAC的电平进行切换，使得测试装置可以处理具有不同模拟输出电平的不同类型的DUT。

公开(公告)号：US06661248B2

公开(公告)日：2003-12-09

申请号：US10145192

申请日：2002-05-15

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura ,  Hisayoshi Hanai

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura ,  Hisayoshi Hanai

IPC分类号： G01R3126

CPC分类号： G01R31/31905 ,  G01R31/3167

摘要： A test-assisting device (BOST device) is provided in the vicinity of a testing circuit board that transmits signals to and receive signals from a semiconductor integrated circuit to be tested, and the D/A converter circuit for testing, the A/D converter circuit for testing, the measured-data memory, and the analyzing portion of the test-assisting device are carried by separate circuit boards.

摘要翻译： 在测试电路板附近提供一个测试辅助设备（BOST设备），该测试电路板向要测试的半导体集成电路和用于测试的D / A转换器电路发送信号并从其接收信号，A / D转换器 测试电路，测量数据存储器和测试辅助设备的分析部分由独立的电路板承载。