公开(公告)号：US06934648B2

公开(公告)日：2005-08-23

申请号：US10364500

申请日：2003-02-12

申请人： Hisayoshi Hanai ,  Teruhiko Funakura ,  Hisaya Mori

发明人： Hisayoshi Hanai ,  Teruhiko Funakura ,  Hisaya Mori

IPC分类号： G01R29/02 ,  G01R29/26 ,  G01R31/28 ,  G06F19/00 ,  H04B17/00

CPC分类号： G01R29/26

摘要： A jitter measurement circuit includes: a conversion section sampling one of a reference signal and a measurement target signal in response to the other of the signals, thereby obtaining a sampling data string; and a determination section measuring jitter of the measurement target signal on the basis of the sampling data string obtained by the conversion section. Since the reference signal is a stable signal having a predetermined cycle, the sampling data string as a measurement result depends on the measurement target signal. Therefore, it is possible to simply measure jitter level in accordance with irregularity of the measurement result and on the basis of relative measurement to expected value data.

摘要翻译： 抖动测量电路包括：响应于另一个信号对参考信号和测量目标信号之一进行采样的转换部分，从而获得采样数据串; 以及确定部，其基于由转换部获得的采样数据串来测量测量目标信号的抖动。 由于参考信号是具有预定周期的稳定信号，作为测量结果的采样数据串取决于测量目标信号。 因此，可以根据测量结果的不规则性和基于对期望值数据的相对测量来简单地测量抖动水平。

公开(公告)号：US07058865B2

公开(公告)日：2006-06-06

申请号：US10647267

申请日：2003-08-26

申请人： Hisaya Mori ,  Teruhiko Funakura ,  Hisayoshi Hanai

发明人： Hisaya Mori ,  Teruhiko Funakura ,  Hisayoshi Hanai

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/56 ,  G01R31/31905 ,  G01R31/31919 ,  G01R31/31926 ,  G06F11/263

摘要： An apparatus for testing a semiconductor integrated circuit has a test circuit board and an ancillary test device. The ancillary test device can test a digital circuit. The ancillary test device has test pattern memory, a test pattern signal generator, and a control section for controlling an operation for the test pattern data selected from among the plurality of test pattern data sets stored in the test pattern memory and an operation for writing the selected test pattern data into the test pattern signal generator. The ancillary test device generates a test input pattern signal on the basis of test pattern data written in the test pattern signal generator and determines a test output pattern signal output from the semiconductor integrated circuit on the basis of the test input pattern signal, thereby testing a digital circuit.

摘要翻译： 用于半导体集成电路测试的装置具有测试电路板和辅助测试装置。 辅助测试设备可以测试数字电路。 辅助测试装置具有测试模式存储器，测试模式信号发生器和用于控制从存储在测试模式存储器中的多个测试模式数据集中选择的测试模式数据的操作的控制部分，以及用于写入 将测试图案数据选入测试图形信号发生器。 辅助测试装置根据写在测试图形信号发生器中的测试图案数据产生测试输入模式信号，并且基于测试输入模式信号确定从半导体集成电路输出的测试输出模式信号，从而测试 数字电路。

公开(公告)号：US06661248B2

公开(公告)日：2003-12-09

申请号：US10145192

申请日：2002-05-15

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura ,  Hisayoshi Hanai

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura ,  Hisayoshi Hanai

IPC分类号： G01R3126

CPC分类号： G01R31/31905 ,  G01R31/3167

摘要： A test-assisting device (BOST device) is provided in the vicinity of a testing circuit board that transmits signals to and receive signals from a semiconductor integrated circuit to be tested, and the D/A converter circuit for testing, the A/D converter circuit for testing, the measured-data memory, and the analyzing portion of the test-assisting device are carried by separate circuit boards.

摘要翻译： 在测试电路板附近提供一个测试辅助设备（BOST设备），该测试电路板向要测试的半导体集成电路和用于测试的D / A转换器电路发送信号并从其接收信号，A / D转换器 测试电路，测量数据存储器和测试辅助设备的分析部分由独立的电路板承载。

公开(公告)号：US06651023B2

公开(公告)日：2003-11-18

申请号：US09927367

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G06F1300

CPC分类号： G01R31/31919 ,  G01R31/3167 ,  G01R31/31935

摘要： A semiconductor test apparatus includes an analog-to-digital converter for converting into a digital signal an analog output from a circuit under test; a test-apparatus-ADC-control-signal generation circuit for generating a control signal for the analog-to-digital converter in accordance with an activation signal entered from the outside; a measured data memory for storing, as measured data for each conversion, a signal output from the analog-to-digital converter; an address counter for generating an address signal for the measured data memory; a DAC counter for generating data to be input to the circuit under test; and a data write control circuit which produces, in response to a flag signal output from the analog-to-digital converter and representing that conversion is being performed, an update signal for the address counter, a memory write signal for the measured data memory, and an update signal for the DAC counter.

公开(公告)号：US06634004B1

公开(公告)日：2003-10-14

申请号：US09706696

申请日：2000-11-07

申请人： Shinji Yamada ,  Hisaya Mori ,  Teruhiko Funakura

发明人： Shinji Yamada ,  Hisaya Mori ,  Teruhiko Funakura

IPC分类号： G11C2900

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C16/34 ,  G11C29/50 ,  G11C2029/5604 ,  G11C2029/5606

摘要： In a threshold analysis method obtaining threshold voltages of all bits in a flash memory through single processing, fail bit map information is examined in order from a smaller voltage applied to the flash memory. As to a bit exhibiting a value, read from the flash memory, first mismatching a determination value, the threshold voltage is settled on the basis of a voltage applied when the bit fails in reading.

摘要翻译： 在通过单个处理获得闪存中的所有位的阈值电压的阈值分析方法中，从施加到闪速存储器的较小电压的顺序检查故障位图信息。 对于显示一个值的位，从闪速存储器中读出，首先使确定值不匹配，阈值电压基于读取位故障时施加的电压来确定。

公开(公告)号：US06690189B2

公开(公告)日：2004-02-10

申请号：US09927404

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G01R3102

CPC分类号： H03M1/1071 ,  H03M1/66

摘要： There are provided a test apparatus and method for testing a semiconductor integrated circuit which enables improvements in the ease of operation and convenience of a BOST device and shortening of a test time. Numeric codes are assigned to tests. A test apparatus is equipped with memory and an analysis section. A test requirement table—in which hardware requirements required for conducting a test are set on a per-numeric-code basis—is stored in the memory. Test requirements corresponding to a numeric code are read from the memory, whereupon a test is performed. The analysis section analyzes a digital test output and sends the result of analysis to an external controller.

摘要翻译： 提供了一种用于测试半导体集成电路的测试装置和方法，其能够改善BOST设备的操作的便利性和便利性，并缩短测试时间。 数字代码被分配给测试。 测试装置配备有记忆和分析部分。 测试要求表（其中进行测试所需的硬件要求以每数字代码为基础设置）存储在存储器中。 从存储器读取对应于数字代码的测试要求，然后进行测试。 分析部分分析数字测试输出，并将分析结果发送给外部控制器。

公开(公告)号：US06587975B2

公开(公告)日：2003-07-01

申请号：US09346268

申请日：1999-07-01

申请人： Hisaya Mori ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Teruhiko Funakura

IPC分类号： G11C2900

CPC分类号： G11C29/56 ,  G11C16/04 ,  G11C2029/5606

摘要： A semiconductor test apparatus and method for performing a test on a nonvolatile semiconductor memory such as a flash memory while preventing excessive erasing with reliability. In each erase operation, all addresses are scanned to fetch an error address and error data into a catch memory. Then, on the basis of error information (error address and error data), a rewrite operation is performed to write data on all memory cells. The write data varies according to a comparison result between an address signal and an error address signal. If they disagree, a “0” is written on a memory cell at the address. If they agree, a “0” is written on a “pass” memory cell and a “1” is virtually written on a fail memory cell.

摘要翻译： 一种用于在诸如闪存之类的非易失性半导体存储器上执行测试的半导体测试装置和方法，同时可靠地防止过度擦除。 在每个擦除操作中，扫描所有地址以将错误地址和错误数据提取到捕获存储器中。 然后，基于错误信息（错误地址和错误数据），执行重写操作以将数据写入所有存储器单元。 写入数据根据地址信号和错误地址信号之间的比较结果而变化。 如果它们不同意，则在地址上的存储单元上写入“0”。 如果它们同意，则在“通过”存储单元上写入“0”，并且虚拟地将“1”写入故障存储单元。

公开(公告)号：US06653855B2

公开(公告)日：2003-11-25

申请号：US09927366

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G01R3102

CPC分类号： G01R31/319

摘要： A BOST (built-off self-test) board has a connector, a substrate for use with a BOST board, and an external self-test circuit. The external self-test circuit has an ADC (analog-to-digital converter)/DAC (digital-to-analog converter) measurement section and a DSP (digital signal processor). In accordance with a control signal input by way of a specific terminal provided in a connector, the ADC/DAC measurement section transmits a predetermined test signal to the specific terminal provided in the connector. Further, in response to the test signal, the ADC/DAC measurement section receives a response signal input to the specific terminal provided in the connector. The DSP analysis section analyzes the response signal, thereby determining whether or not the response signal is an appropriate signal. Further, the DSP analysis section transmits, to the specific terminal provided in the connector, a test result signal indicating whether or not the response signal is appropriate.

公开(公告)号：US06628137B2

公开(公告)日：2003-09-30

申请号：US09927471

申请日：2001-08-13

申请人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

发明人： Hisaya Mori ,  Shinji Yamada ,  Teruhiko Funakura

IPC分类号： G01R3126

CPC分类号： G01R31/31926

摘要： There are provided a test apparatus and a test method for testing a semiconductor integrated circuit which facilitate control of a BOST device and improve the versatility of the BOST device. There is provided an interface for exchanging signals between a BOST device and an external controller. A test control signal and a test result analysis signal are exchanged by means of the interface, thus effecting a test and analysis of the test.

公开(公告)号：US07079060B2

公开(公告)日：2006-07-18

申请号：US11048723

申请日：2005-02-03

申请人： Toshiaki Tarui ,  Masaru Sugimoto ,  Hisaya Mori ,  Teruhiko Funakura

发明人： Toshiaki Tarui ,  Masaru Sugimoto ,  Hisaya Mori ,  Teruhiko Funakura

IPC分类号： H03M1/12

CPC分类号： G01R31/31924 ,  G01R19/257 ,  G01R29/0276

摘要： In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.

摘要翻译： 在测试电路中，确定电路进行功能测试，以确定测量目标器件的模拟信号ANS的波形的斜率部分的定时是否在规格范围内。 只有当模拟信号ANS的电位在参考电位VOL，VOH之间的范围内时，ADC才执行AD转换。 分析单元从ADC分析数字数据，并进行倾斜波形测试，以评估模拟信号ANS波形的倾斜状态。 因此，可以在不需要大容量存储电路的情况下，在任意电压幅度的范围内，以任意数量的区间划分的装置的模拟信号ANS的波形的斜率部分进行AD转换。 可以并行地执行由判定电路进行的功能测试和分析单元的倾斜波形测试。