公开(公告)号：US08526897B2

公开(公告)日：2013-09-03

申请号：US12938451

申请日：2010-11-03

Applicant: Matthew Henson

Inventor： Matthew Henson

IPC: H04B1/18

CPC classification number: H04W52/0229 ,  H04H2201/18 ,  Y02D70/00

Abstract: According to one aspect of the present invention, a controller is coupled to at least first and second signal processors (at least one of which includes analog demodulation circuitry and another of which includes digital demodulation circuitry). The controller may operate to disable the first signal processor responsive to a control signal that indicates that a second signal (corresponding to a demodulator output) is available from the second signal processor.

Abstract translation: 根据本发明的一个方面，控制器耦合到至少第一和第二信号处理器（其中至少一个包括模拟解调电路，另一个包括数字解调电路）。 控制器可以操作以响应于指示来自第二信号处理器的第二信号（对应于解调器输出）的控制信号来禁用第一信号处理器。

公开(公告)号：US07725759B2

公开(公告)日：2010-05-25

申请号：US11170475

申请日：2005-06-29

Applicant: Matthew Henson

Inventor： Matthew Henson

IPC: G06F1/08 ,  G06F13/366

CPC classification number: G06F1/3203 ,  G06F1/324 ,  Y02D10/126

Abstract: A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input from at least one of the plurality of master devices. The input can be a request an increase to the clock frequency of the bus. Further, the method includes selectively increasing the clock frequency of the bus in response to the request.

Abstract translation: 公开了一种控制时钟频率的方法，并且包括监视耦合到系统内的总线的多个主设备。 该方法还包括接收来自多个主设备中的至少一个的输入。 输入可以是增加总线时钟频率的请求。 此外，该方法包括响应于该请求选择性地增加总线的时钟频率。

公开(公告)号：US07555591B2

公开(公告)日：2009-06-30

申请号：US11118587

申请日：2005-04-29

Applicant: Russell Alvin Schultz ,  David A. Moore ,  Matthew Henson

Inventor： Russell Alvin Schultz ,  David A. Moore ,  Matthew Henson

IPC: G06F12/08

CPC classification number: G06F12/1045 ,  G06F12/0842 ,  G06F12/12 ,  G06F2212/2022

Abstract: The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to the processor. The processor is configured to access a virtual memory space to perform a first task and is configured to access the virtual memory space to perform a second task. The virtual memory space references first and second sets of task instructions associated with the first and second tasks, respectively. The virtual memory space references non-instruction data associated with the first task. The cache memory is configured to store the first set of task instructions and the non-instruction data. The memory management unit is configured to determine the physical memory location of the second set of task instructions. The computational system is configured to not write the first set of task instructions and the non-instruction data to a physical location beyond the cache memory.

Abstract translation: 本公开涉及包括处理器，处理器可访问的高速缓存存储器和处理器可访问的存储器管理单元的计算系统。 处理器被配置为访问虚拟存储器空间以执行第一任务，并且被配置为访问虚拟存储器空间以执行第二任务。 虚拟存储器空间分别引用与第一和第二任务相关联的第一组和第二组任务指令。 虚拟内存空间引用与第一个任务相关联的非指令数据。 缓存存储器被配置为存储第一组任务指令和非指令数据。 存储器管理单元被配置为确定第二组任务指令的物理存储器位置。 计算系统被配置为不将第一组任务指令和非指令数据写入高速缓冲存储器之外的物理位置。

公开(公告)号：US07529878B2

公开(公告)日：2009-05-05

申请号：US11118593

申请日：2005-04-29

Applicant: Russell Alvin Schultz ,  David A. Moore ,  Matthew Henson

Inventor： Russell Alvin Schultz ,  David A. Moore ,  Matthew Henson

IPC: G06F12/08

CPC classification number: G06F12/10 ,  G06F12/1045 ,  G06F2212/656 ,  Y02D10/13

Abstract: The disclosure is directed to a computational system including a processor and a memory management unit accessible to the processor. The processor is configured to access a common virtual memory space to perform a first task of a plurality of tasks and is configured to access the common virtual memory space to perform a second task of the plurality of tasks. The common virtual memory space references a first set of instructions associated with the first task and references a second set of instructions associated with the second task. The memory management unit is configured to determine a physical memory location of at least one of the first and second sets of instructions when the associated first or second task is to be performed by the processor.

Abstract translation: 本发明涉及一种包括处理器和可由处理器访问的存储器管理单元的计算系统。 处理器被配置为访问公共虚拟存储器空间以执行多个任务的第一任务，并且被配置为访问公共虚拟存储器空间以执行多个任务的第二任务。 公共虚拟存储器空间引用与第一任务相关联的第一组指令并引用与第二任务相关联的第二组指令。 存储器管理单元被配置为当处理器执行相关联的第一或第二任务时，确定第一组和第二组指令中的至少一个的物理存储器位置。

公开(公告)号：US07428603B2

公开(公告)日：2008-09-23

申请号：US11171919

申请日：2005-06-30

Applicant: Matthew Henson ,  David Cureton Baker

Inventor： Matthew Henson ,  David Cureton Baker

IPC: G06F13/28

CPC classification number: G06F13/1694

Abstract: The disclosure is directed to a device including a memory interface. The memory interface includes a data interface, a first state machine and a second state machine. The first state machine includes a first chip select interface and a first ready/busy interface. The first state machine is configured to select and monitor a first memory device via the first chip select interface and the first ready/busy interface, respectively, when the first memory device is coupled to the data interface. The second state machine includes a second chip select interface and a second ready/busy inter-face. The second state machine is configured to select and monitor a second memory device via the second chip select interface and the second ready/busy interface, respectively, when the second memory device is coupled to the data interface.

Abstract translation: 本公开涉及包括存储器接口的设备。 存储器接口包括数据接口，第一状态机和第二状态机。 第一状态机包括第一芯片选择接口和第一就绪/忙碌接口。 第一状态机被配置为当第一存储器设备耦合到数据接口时，分别经由第一芯片选择接口和第一就绪/忙接口来选择和监视第一存储器设备。 第二状态机包括第二芯片选择接口和第二就绪/忙碌接口。 第二状态机被配置为当第二存储器设备耦合到数据接口时，分别经由第二芯片选择接口和第二就绪/忙接口来选择和监视第二存储器设备。

公开(公告)号：US20070191073A1

公开(公告)日：2007-08-16

申请号：US11355477

申请日：2006-02-16

Applicant: Michael May ,  Marcus May ,  Matthew Henson

Inventor： Michael May ,  Marcus May ,  Matthew Henson

IPC: H04B1/38

CPC classification number: H04B15/005 ,  H04B2215/068

Abstract: A method for mitigating interference from a switched-mode power supply begins by comparing a channel of interest of a plurality of channels with a switching rate of a switch-mode power supply. The method continues when the channel of interest compares unfavorably to the switching rate by adjusting the switching rate of the switch-mode power supply until the channel of interest compares favorably to the switching rate.

Abstract translation: 通过将多个信道的感兴趣信道与开关模式电源的切换速率进行比较，开始减少来自开关模式电源的干扰的方法。 当感兴趣的信道通过调整开关模式电源的切换速率直到感兴趣的信道与切换速率有利地相比，当感兴趣的信道与切换速率不利地相比时，继续该方法。

公开(公告)号：US20070173287A1

公开(公告)日：2007-07-26

申请号：US11340441

申请日：2006-01-26

Applicant: Matthew Henson ,  Thomas Ragan

Inventor： Matthew Henson ,  Thomas Ragan

IPC: H04B1/38

CPC classification number: H04W52/0264 ,  H04B2001/3866 ,  H04M1/677 ,  H04M1/72558 ,  Y02D70/1224 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/23

Abstract: A wireless handset includes a long range wireless transceiver for selectively providing an inbound communication and an outbound communication through a wireless telephone network. A battery monitor module monitors a remaining power of a battery and produces a control signal when the remaining power compares unfavorably to a reserve power threshold. A processing module allows an outbound communication to an allowed recipient when the control signal is asserted, and prohibits an outbound communication to a disallowed recipient when the control signal is asserted.

Abstract translation: 无线手机包括用于选择性地通过无线电话网络提供入站通信和出站通信的远程无线收发器。 电池监视器模块监视电池的剩余电量，并且当剩余功率与预留功率阈值不利地相比时产生控制信号。 当控制信号被断言时，处理模块允许到允许的接收者的出站通信，并且当控制信号被断言时，禁止与不允许的接收者的出站通信。

公开(公告)号：US20070055462A1

公开(公告)日：2007-03-08

申请号：US11494781

申请日：2006-07-27

Applicant: Daniel Mulligan ,  Marcus May ,  Matthew Henson ,  Debby Clarke

Inventor： Daniel Mulligan ,  Marcus May ,  Matthew Henson ,  Debby Clarke

IPC: G01B5/28

CPC classification number: H04N7/148 ,  H04N21/41407 ,  H04N21/4223 ,  H04N21/4325

Abstract: A circuit for use by a multifunction handheld device is coupleable to an audio output device, the multifunction handheld device including, a color video display device, and a host interface that is coupleable to a host device. The circuit includes a host interface that is coupleable to a host device, wherein the host interface includes a wireless communication link for communicating with the host device via a wireless local area network protocol. The circuit further includes a processing module and a memory interface, operably coupled to the processing module and a memory that stores a plurality of digitally formatted files, and that stores operational instructions that cause the processing module to: receive a first digitally formatted file of the plurality of digitally formatted files from the host device when coupled to the host device via the host interface and store the first digitally formatted file in the memory, wherein the first digitally formatted file includes a compressed audio file; receive a second digitally formatted file of the plurality of digitally formatted files from a host device when coupled to the host device via a host interface and store the second digitally formatted file in the memory, wherein the second digitally formatted file includes a compressed video file; and playback a selected one of the plurality of digitally formatted files, the playback including the generation of an audio output signal for the audio output device, when the first digitally formatted file is selected, and the playback including rendering the selected one of the digitally formatted files for the color video display device, when the first digitally formatted file is selected.

Abstract translation: 由多功能手持设备使用的电路可耦合到音频输出设备，多功能手持设备包括彩色视频显示设备和可与主机设备耦合的主机接口。 电路包括可与主机设备耦合的主机接口，其中主机接口包括用于经由无线局域网协议与主机设备进行通信的无线通信链路。 电路还包括可操作地耦合到处理模块的处理模块和存储器接口，以及存储多个数字格式的文件的存储器，并且存储操作指令，该操作指令使处理模块：接收第一数字格式的文件 当通过主机接口耦合到主机设备时，来自主机设备的多个数字格式的文件，并将第一数字格式化的文件存储在存储器中，其中第一数字格式化文件包括压缩音频文件; 当经由主机接口耦合到所述主机设备时，从所述主机设备接收所述多个数字格式化文件的第二数字格式化文件，并将所述第二数字格式文件存储在所述存储器中，其中所述第二数字格式化文件包括压缩视频文件; 并且当选择所述第一数字格式化文件时，播放所述多个数字格式化文件中的所选择的一个，所述播放包括用于所述音频输出设备的音频输出信号的生成，并且所述播放包括渲染所选择的数字格式化的 当选择第一个数字格式的文件时，彩色视频显示设备的文件。

公开(公告)号：US07864962B2

公开(公告)日：2011-01-04

申请号：US11170487

申请日：2005-06-29

Applicant: Matthew Henson ,  Daniel Mulligan

Inventor： Matthew Henson ,  Daniel Mulligan

IPC: H04H40/81 ,  H04B3/00

CPC classification number: H04R5/02

Abstract: A method and system for utilizing multiple speakers in a portable electronic device is disclosed. The method includes receiving an input at a user interface of a portable electronic device, switching a first and second speaker in a stereo configuration to a mono configuration by routing a first digital to analog converter (DAC) output to both the first and second speaker in response to the input and coupling a third speaker to a second DAC to receive a first audio signal that is responsive to the input. The system includes a first digital to analog converter coupled to a first speaker, a second DAC coupled to a second speaker, and a third speaker. The system further includes switching logic coupled to the first and second DACs. The switching logic is responsive to an input signal provided by a user interface of a portable device. In response to an input signal from the user interface, the switching logic couples the first and second speakers to the first DAC and the third speaker to the second DAC.

Abstract translation: 公开了一种在便携式电子设备中使用多个扬声器的方法和系统。 该方法包括在便携式电子设备的用户接口处接收输入，通过将第一和第二扬声器输出到第一和第二扬声器的方式将第一和第二扬声器以立体声配置切换为单声道配置， 响应于所述输入并将第三扬声器耦合到第二DAC以接收响应于所述输入的第一音频信号。 该系统包括耦合到第一扬声器的第一数模转换器，耦合到第二扬声器的第二DAC和第三扬声器。 该系统还包括耦合到第一和第二DAC的开关逻辑。 开关逻辑响应由便携式设备的用户界面提供的输入信号。 响应于来自用户接口的输入信号，开关逻辑将第一和第二扬声器耦合到第一DAC和第三扬声器到第二DAC。

公开(公告)号：US20080022236A1

公开(公告)日：2008-01-24

申请号：US11852759

申请日：2007-09-10

Applicant: Matthew Henson ,  Matthew Felder ,  Marcus May ,  Daniel Mulligan

Inventor： Matthew Henson ,  Matthew Felder ,  Marcus May ,  Daniel Mulligan

IPC: G06F17/50

CPC classification number: G06F1/26 ,  H02J7/0065 ,  H04M1/72522 ,  H04W52/0229

Abstract: A system-on-a-chip integrated circuit includes a multimedia module that produces rendered output data and a high-speed interface. A processing module generates output multimedia data in accordance with at least a portion of a multimedia application in response to input multimedia data received from either the multimedia module or the high-speed interface. The output multimedia data is provided to either the multimedia module or the high-speed interface. An on-chip DC-to-DC converter converts a battery voltage into a supply voltage that is coupled to the multimedia module, the high-speed interface, and/or the processing module.

Abstract translation: 片上系统集成电路包括产生渲染输出数据和高速接口的多媒体模块。 响应于从多媒体模块或高速接口接收的输入多媒体数据，处理模块根据多媒体应用的至少一部分生成输出多媒体数据。 输出多媒体数据被提供给多媒体模块或高速接口。 片上DC-DC转换器将电池电压转换成耦合到多媒体模块，高速接口和/或处理模块的电源电压。