公开(公告)号：US20070072574A1

公开(公告)日：2007-03-29

申请号：US11237339

申请日：2005-09-28

Applicant: Thomas Ragan ,  Matthew Felder ,  Michael May

Inventor： Thomas Ragan ,  Matthew Felder ,  Michael May

IPC: H04B1/26

CPC classification number: H04B1/28

Abstract: A receiver includes a mixing module for mixing an input signal by at least one mixing sequence to produce a mixed signal. The mixed signal is filtered to produce a first filtered signal. A first downsampler downsamples the first filtered signal to produce a first decimated signal, wherein the decimation period is not a multiple of the mixing period.

Abstract translation: 接收机包括混合模块，用于通过至少一个混合序列混合输入信号以产生混合信号。 对混合信号进行滤波以产生第一滤波信号。 第一下采样器对第一滤波信号进行下采样以产生第一抽取信号，其中抽取周期不是混合周期的倍数。

公开(公告)号：US20070069939A1

公开(公告)日：2007-03-29

申请号：US11498204

申请日：2006-08-01

Applicant: Matthew Felder ,  Michael May

Inventor： Matthew Felder ,  Michael May

IPC: H03M1/12

CPC classification number: H03M3/35 ,  H03M3/496

Abstract: A controlled sampling module samples an input signal from an input device and a reference signal. The controlled sampling module includes a plurality of sample capacitors, a switching network, and a switch control module for controlling the switching network. The switching network couples a first capacitor of the plurality of capacitors to the reference signal during a first phase, and to the input signal during a second phase, such that a charge on the first capacitor remaining at an end of the first phase is cancelled during the second phase.

Abstract translation: 受控采样模块从输入设备和参考信号采样输入信号。 受控采样模块包括多个采样电容器，开关网络和用于控制开关网络的开关控制模块。 开关网络在第一阶段期间将多个电容器中的第一电容器耦合到参考信号，并且在第二阶段期间耦合到输入信号，使得在第一阶段结束时剩余的第一电容器上的电荷被消除 第二阶段

公开(公告)号：US20060285702A1

公开(公告)日：2006-12-21

申请号：US11155459

申请日：2005-06-17

Applicant: Matthew Felder

Inventor： Matthew Felder

IPC: H04R3/00

CPC classification number: H04R3/12 ,  H04R2420/05 ,  H04R2499/11

Abstract: A multi-mode driver circuit includes a first channel driver, a second channel driver, and a control module. The first channel driver module is operably coupled to drive a first channel signal to a first node of an output. The second channel driver module is operably coupled to drive a second channel signal to a second node of the output. The control module is operably coupled to provide a monotone signal as the first channel signal to the first channel driver module and an inversion of the monotone signal as the second channel signal to the second channel driver module when the multi-mode driver is in a first state. The control module is also operably coupled to provide a first stereo signal as the first channel signal to the first channel driver module and a second stereo signal as the second channel signal to the second channel driver module when the multi-mode driver is in a second state.

Abstract translation: 多模式驱动器电路包括第一通道驱动器，第二通道驱动器和控制模块。 第一通道驱动器模块可操作地耦合以将第一通道信号驱动到输出的第一节点。 第二通道驱动器模块可操作地耦合以将第二通道信号驱动到输出的第二节点。 控制模块可操作地耦合以提供作为第一通道信号的单调信号到第一通道驱动器模块，并且当多模式驱动器处于第一通道驱动器模块时，单调信号作为第二通道信号反转到第二通道驱动器模块 州。 当多模式驱动器处于第二通道时，控制模块还可操作地耦合以将第一立体声信号作为第一通道信号提供给第一通道驱动器模块，并将第二立体声信号作为第二通道信号提供给第二通道驱动器模块 州。

公开(公告)号：US20060132091A1

公开(公告)日：2006-06-22

申请号：US11015538

申请日：2004-12-17

Applicant: Matthew Felder ,  Russell Schultz

Inventor： Matthew Felder ,  Russell Schultz

IPC: H02J7/00

CPC classification number: H02J7/0086

Abstract: A semiconductor device includes an adjustable current source that is coupled to an external battery. The semiconductor device includes a feedback control module that is responsive to a voltage level at the external battery. The feedback control module also has an output that is directed to control the current supplied by the adjustable current source. Also, the feedback control module can selectively provide a signal to periodically and temporarily turn off the current supplied by the adjustable current source. A voltage at the external battery is measured during a time period when the current is turned on and during a time period when the current is turned off. While the current is turned off, the feedback control module can measure the external battery voltage so that it can be compared to the battery voltage while the adjustable current source is on.

公开(公告)号：US20120155586A1

公开(公告)日：2012-06-21

申请号：US12971391

申请日：2010-12-17

Applicant: Matthew Felder ,  Mark Summers

Inventor： Matthew Felder ,  Mark Summers

IPC: H04L7/00

CPC classification number: H03L7/16

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract translation: 本发明的各种实施例涉及对内部产生高频过采样时钟信号的电子部件过采样的系统，装置和方法。 所产生的过采样时钟与串行数据链路中的输入时钟和输入串行数据自动同步，并且适应于诸如位深度和过采样率之类的预定参数。

公开(公告)号：US20070236285A1

公开(公告)日：2007-10-11

申请号：US11402189

申请日：2006-04-11

Applicant: Matthew Felder

Inventor： Matthew Felder

IPC: H03F1/02

CPC classification number: H03F3/38 ,  H03F1/26 ,  H03F3/45183 ,  H03F3/45744 ,  H03F3/45968 ,  H03F2200/372 ,  H03F2200/375 ,  H03F2203/45588 ,  H03F2203/45616 ,  H03F2203/45681 ,  H03F2203/45726 ,  H03K5/2481 ,  H03K5/249

Abstract: An amplifying circuit includes an input chopping circuit, an amplifier, and an output chopping circuit. The input chopping circuit is operably coupled to chop an input signal at a chopping rate to produce a chopped input signal. The amplifier has a first input transistor section, a second input transistor section, and a transistor load section. The first and second input transistor sections are operably coupled to receive the chopped input signal, wherein the first input transistor section amplifies the chopped input signal when the chopped input signal is in first signal level range, the second input transistor section amplifies the chopped input signal when the chopped input signal is in a second signal level range, and the first and second input transistor sections amplify the chopped input signal when the chopped input signal is in a third signal level range, wherein the transistor load section is coupled to the first and second input transistors sections to produce an amplified chopped signal. The output chopping circuit is operably coupled to chop the amplified chopped signal at the chopping rate to produce an amplified output signal.

Abstract translation: 放大电路包括输入斩波电路，放大器和输出斩波电路。 输入斩波电路可操作地耦合以以斩波速率斩波输入信号以产生斩波输入信号。 放大器具有第一输入晶体管部分，第二输入晶体管部分和晶体管负载部分。 第一和第二输入晶体管部分可操作地耦合以接收斩波输入信号，其中当斩波输入信号处于第一信号电平范围时，第一输入晶体管部分放大斩波输入信号，第二输入晶体管部分放大斩波输入信号 当所述斩波输入信号处于第二信号电平范围时，并且当所述斩波输入信号处于第三信号电平范围时，所述第一和第二输入晶体管部放大所述斩波输入信号，其中所述晶体管负载部分耦合到所述第一信号电平范围， 第二输入晶体管部分以产生放大的切碎信号。 输出斩波电路可操作地耦合以以斩波速率斩波放大的斩波信号以产生放大的输出信号。

公开(公告)号：US20070223631A1

公开(公告)日：2007-09-27

申请号：US11388675

申请日：2006-03-24

Applicant: Matthew Felder ,  Michael May

Inventor： Matthew Felder ,  Michael May

IPC: H04L27/08

CPC classification number: H04L27/14 ,  H03F3/189 ,  H03F3/343 ,  H03G3/3068

Abstract: A method for signal strength detection begins by comparing a signal strength representation of a signal with a signal strength representation of a reference signal. The method continues by adjusting, when the signal strength representation of the signal compares unfavorably with the signal strength representation of the reference signal, at least one of the signal strength representation of the signal and the signal strength representation of the reference signal until the signal strength representation of the signal compares favorably with the signal strength representation of the reference signal. The method continues by determining signal strength of the signal based on the adjusting of the signal strength representation of the signal and signal strength of the reference signal.

Abstract translation: 用于信号强度检测的方法开始于将信号的信号强度表示与参考信号的信号强度表示进行比较。 该方法通过调节信号的信号强度表示与参考信号的信号强度表示不利地相比较，信号的信号强度表示和参考信号的信号强度表示中的至少一个直到信号强度 信号的表示与参考信号的信号强度表示相当。 该方法通过基于信号的信号强度表示和参考信号的信号强度的调整来确定信号的信号强度来继续。

公开(公告)号：US20070133809A1

公开(公告)日：2007-06-14

申请号：US11300236

申请日：2005-12-14

Applicant: Matthew Felder

Inventor： Matthew Felder

IPC: H04H5/00

CPC classification number: H04H60/04 ,  G06F3/162 ,  G10L21/0208 ,  H04B1/1036

Abstract: An audio output circuit includes an on-chip left channel amplifier module, an on-chip center channel amplifier module, and an on-chip right channel amplifier module. A left channel IC pin is operably coupled to an output of the on-chip left channel amplifier module. A right channel IC pin is operably coupled to an output of the on-chip right channel amplifier module. A center channel IC pin is operably coupled to an output of the on-chip center channel amplifier module. A center channel feedback IC pin is operably coupled to an input of the on-chip center channel amplifier module to provide a feedback loop. A left jack connection is operably coupled to the left channel IC pin. A right jack connection is operably coupled to the right channel IC pin. A jack return connection coupled to the center feedback IC pin. An inductor has a first node coupled to the jack return connection and a second node coupled to the center channel IC pin.

Abstract translation: 音频输出电路包括片上左声道放大器模块，片上中心声道放大器模块和片上右声道放大器模块。 左通道IC引脚可操作地耦合到片上左声道放大器模块的输出。 右通道IC引脚可操作地耦合到片上右声道放大器模块的输出。 中心通道IC引脚可操作地耦合到片上中心通道放大器模块的输出端。 中心通道反馈IC引脚可操作地耦合到片上中心通道放大器模块的输入端以提供反馈回路。 左插孔连接可操作地耦合到左通道IC引脚。 右插孔连接可操作地耦合到右通道IC引脚。 耦合到中心反馈IC引脚的插座返回连接。 电感器具有耦合到插座返回连接的第一节点和耦合到中心通道IC引脚的第二节点。

公开(公告)号：US20060232461A1

公开(公告)日：2006-10-19

申请号：US11105015

申请日：2005-04-13

Applicant: Matthew Felder

Inventor： Matthew Felder

IPC: H03M1/38

CPC classification number: H03M1/462 ,  H03M1/745

Abstract: A successive approximation Analog-to-Digital Converter (“ADC”) having a successive approximation controller operably coupled to convert a control signal into a digital output of the successive approximation ADC, a current-steered Digital-to-Analog Converter operably coupled to convert the digital output of the successive approximation ADC into an analog feedback signal, and a comparator module operably coupled to compare the analog feedback signal with an analog input of the successive approximation ADC to produce the control signal. A further aspect is a method for increasing accuracy for a digital successive approximation of an analog input signal. The method includes determining a signal characteristic of the analog input signal to an Analog-to-Digital Converter (“ADC”), and selecting a reference voltage source of a Digital-to-Analog Converter of the ADC from a plurality of reference voltage sources based on the analog input signal.

Abstract translation: 具有可操作地耦合以将控制信号转换成逐次逼近ADC的数字输出的逐次逼近控制器的逐次逼近模数转换器（“ADC”），可操作地耦合到转换器的电流转向数字 - 模拟转换器 逐次逼近ADC的数字输出转换为模拟反馈信号，以及可操作地耦合以将模拟反馈信号与逐次逼近ADC的模拟输入进行比较以产生控制信号的比较器模块。 另一方面是用于提高模拟输入信号的数字逐次逼近的精度的方法。 该方法包括确定模拟输入信号到模数转换器（“ADC”）的信号特性，以及从多个参考电压源中选择ADC的数模转换器的参考电压源 基于模拟输入信号。

公开(公告)号：US20060125568A1

公开(公告)日：2006-06-15

申请号：US11009110

申请日：2004-12-10

Applicant: Matthew Felder ,  Marcus May

Inventor： Matthew Felder ,  Marcus May

IPC: H02H7/20

CPC classification number: G05F1/573

Abstract: A current threshold circuit includes a series impedance, a reference voltage source, and a comparison module. The series impedance couples an output of a current source to a load, wherein impedance of the series impedance is substantially less than impedance of the load. The reference voltage source is operably coupled to produce a reference voltage differential. The comparison module is operably coupled to compare the reference voltage differential with a differential voltage of the series impedance, wherein the comparison module generates an excessive current indication when the differential voltage of the series impedance compares unfavorably to the reference voltage differential.

Abstract translation: 电流阈值电路包括串联阻抗，参考电压源和比较模块。 串联阻抗将电流源的输出耦合到负载，其中串联阻抗的阻抗基本上小于负载的阻抗。 参考电压源可操作地耦合以产生参考电压差。 比较模块可操作地耦合以将参考电压差与串联阻抗的差分电压进行比较，其中当串联阻抗的差分电压与参考电压差不利地相比时，比较模块产生过电流指示。