公开(公告)号：US20160241854A1

公开(公告)日：2016-08-18

申请号：US15016221

申请日：2016-02-04

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/13 ,  H04N19/91 ,  H04N19/895 ,  H04N19/176 ,  H04N19/436 ,  H04N19/44 ,  H04N19/48

CPC classification number: H04N19/91

Abstract: An apparatus and method for high-throughput entropy decoding in a video decoder are disclosed. The apparatus comprises an arithmetic decoding processing circuitry and a variable-length decoder (VLD). The arithmetic decoding processing circuitry receives a video bitstream through a bitstream input, applies arithmetic decoding to at least a portion of the video bitstream to derive one or more arithmetic-decoded binary strings containing no arithmetic encoded binary string, and stores the arithmetic-decoded binary strings in the storage device. The variable-length decoder (VLD) is coupled to the arithmetic decoding processing circuitry, the storage device and a VLD output. The variable-length decoder receives at least a portion of arithmetic-decoded bitstream when arithmetic-decoded bitstreams stored in the storage device are complete for a selected image unit, decodes at least a portion of arithmetic-decoded bitstream into one or more decoded syntax elements, and provides the decoded syntax elements through the VLD output.

Abstract translation: 公开了一种用于视频解码器中高吞吐量熵解码的装置和方法。 该装置包括算术解码处理电路和可变长度解码器（VLD）。 算术解码处理电路通过比特流输入接收视频比特流，对视频比特流的至少一部分应用算术解码以导出不包含算术编码二进制串的一个或多个算术解码二进制串，并存储算术解码二进制码 存储设备中的字符串。 可变长度解码器（VLD）耦合到算术解码处理电路，存储设备和VLD输出。 可变长度解码器在对存储设备中存储的算术解码比特流对于所选择的图像单元是完整的时，接收算术解码比特流的至少一部分，将至少一部分算术解码的比特流解码为一个或多个解码的语法元素 ，并通过VLD输出提供经解码的语法元素。

公开(公告)号：US20140192899A1

公开(公告)日：2014-07-10

申请号：US14142929

申请日：2013-12-30

Applicant: MEDIATEK INC.

Inventor： Chih-Ming Wang ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/593 ,  H04N19/174

CPC classification number: H04N19/70 ,  H04N19/169 ,  H04N19/174 ,  H04N19/44

Abstract: A tile processing method includes at least the following steps: parsing a bitstream of at least a multi-tile picture for deriving bitstream address related information from a segment header of at least a specific segment of the multi-tile picture; and utilizing a tile processing circuit for receiving at least the bitstream address related information and referring to at least the received bitstream address related information to determine a bitstream start address of a specific tile of the multi-tile picture.

Abstract translation: 瓦片处理方法至少包括以下步骤：解析至少多瓦片图像的比特流，以从多瓦片图片的至少特定片段的片段标题导出比特流地址相关信息; 以及利用瓦片处理电路来至少接收所述比特流地址相关信息，并且至少参考所接收的比特流地址相关信息，以确定所述多瓦片图像的特定瓦片的位流起始地址。

公开(公告)号：US20140133580A1

公开(公告)日：2014-05-15

申请号：US14165599

申请日：2014-01-28

Applicant: MEDIATEK INC.

Inventor： Yung-Chang Chang ,  Chia-Yun Cheng ,  Chi-Cheng Ju

IPC: H04N19/44

CPC classification number: H04N19/00533 ,  H04N19/423 ,  H04N19/433 ,  H04N19/44 ,  H04N19/577 ,  H04N19/59

Abstract: A video decoding method for decoding a bit stream to a plurality of frames, applied in a video decoding system, includes: determining whether a size of a current picture is equal to that of a next picture according to the bit stream; scaling a corresponding reference frame for the next picture to generate a scaled frame when the size of the current picture is not equal to that of the next picture; and storing the scaled frame in a first buffer of a storage unit, wherein at least a portion of a first frame originally stored in the first buffer is used; wherein when it is determined that the size of the current picture is not equal to that of the next picture, the next picture is encoded in the bit stream in a mode that the scaled corresponding reference frame is required for decoding the next picture.

Abstract translation: 一种视频解码方法，用于将应用于视频解码系统的比特流解码为多个帧，包括：根据比特流确定当前图像的大小是否等于下一图像的大小; 当当前图像的大小不等于下一图像的大小时，缩放下一图像的对应参考帧以产生缩放帧; 并且将缩放的帧存储在存储单元的第一缓冲器中，其中使用原始存储在第一缓冲器中的第一帧的至少一部分; 其中当确定当前画面的尺寸不等于下一画面的尺寸时，下一画面以对于下一画面进行解码所需的缩放对应的参考帧的模式被编码在比特流中。

公开(公告)号：US11025947B2

公开(公告)日：2021-06-01

申请号：US16697119

申请日：2019-11-26

Applicant: MEDIATEK INC.

Inventor： Yung-Chang Chang ,  Chia-Yun Cheng ,  Cheng-Han Li ,  Hong-Cheng Lin ,  Chi-Hung Chen

IPC: H04N19/52 ,  H04N19/119 ,  H04N19/176

Abstract: A motion vector (MV) projection method includes generating motion field motion vectors (MFMVs) for a first portion of a current frame by applying MV projection to MVs of a portion of each of reference frames and storing the MFMVs of the first portion of the current frame into an MFMV buffer, and generating MFMVs for a second portion of the current frame by applying MV projection to MVs of a portion of each of the reference frames and storing the MFMVs of the second portion of the current frame into the MFMV buffer. The second portion does not overlap the first portion. Before generating the MFMVs for the second portion of the current frame is done, at least one of the MFMVs of the first portion is read from the MFMV buffer and involved in motion vector determination of at least one coding block included in the first portion.

公开(公告)号：US10984832B2

公开(公告)日：2021-04-20

申请号：US16734384

申请日：2020-01-05

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: G11B20/10 ,  H04N19/423 ,  H04N21/44 ,  H04N21/434 ,  H04N21/435 ,  H04N21/4363 ,  G09G5/393

Abstract: A video processing system includes a storage device, a receiving circuit, an audio/video demultiplexing circuit, a video decoder, and a display engine. The storage device includes a data buffer, a bitstream buffer, and a display buffer. An output of the receiving circuit is written into the data buffer. An input of the audio/video demultiplexing circuit is read from the data buffer, and an output of the audio/video demultiplexing circuit is written into the bitstream buffer. An input of the video decoder is read from the bitstream buffer, and an output of the video decoder is written into the display buffer. An input of the display engine is read from the display buffer. Each of the data buffer, the bitstream buffer, and the display buffer is a ring buffer.

公开(公告)号：US20200154108A1

公开(公告)日：2020-05-14

申请号：US16677598

申请日：2019-11-07

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/13 ,  H04N19/44 ,  H04N19/70 ,  H04N19/172 ,  G06F9/38

Abstract: An entropy decoding apparatus includes an entropy decoding circuit, a pre-fetch circuit, and a context pre-load buffer. The pre-fetch circuit pre-fetches at least one candidate context for entropy decoding of a part of an encoded bitstream of a frame before the entropy decoding circuit starts entropy decoding of the part of the encoded bitstream of the frame. The context pre-load buffer buffers the at least one candidate context. When a target context actually needed by entropy decoding of the part of the encoded bitstream of the frame is not available in the context pre-load buffer, the context pre-load buffer instructs the pre-fetch circuit to re-fetch the target context, and the entropy decoding circuit stalls entropy decoding of the part of the encoded bitstream of the frame.

公开(公告)号：US20180152727A1

公开(公告)日：2018-05-31

申请号：US15578191

申请日：2016-06-03

Applicant: MEDIATEK INC.

Inventor： Tzu-Der CHUANG ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Ching-Yeh Chen ,  Yu-Chen Sun ,  Yu-Wen Huang

IPC: H04N19/563 ,  H04N19/593 ,  H04N19/513 ,  H04N19/70

CPC classification number: H04N19/563 ,  H04N19/513 ,  H04N19/593 ,  H04N19/70

Abstract: In order to overcome the issue caused by a decoded block vector (BV) pointing to a reference block overlapping with an unavailable area, various methods are disclosed. According to one method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by padding from neighbouring available pixels. The padding can be done in the horizontal direction and then the vertical direction. The padding may also done in the vertical direction first and then horizontal direction. In another method, if the reference block overlaps with an unavailable area, the reference pixels in the unavailable area are generated for IntraBC prediction of the current block by using previous decoded pixels in the unavailable area. A pre-defined value may also be used for the unavailable area.

公开(公告)号：US20180152714A1

公开(公告)日：2018-05-31

申请号：US15578221

申请日：2016-06-03

Applicant: MEDIATEK INC.

Inventor： Yu-Chen SUN ,  Tzu-Der CHUANG ,  Han-Liang CHOU ,  Chia-Yun Cheng ,  Ching-Yeh CHEN ,  Yu-Wen Huang

IPC: H04N19/186 ,  H04N19/176 ,  H04N19/70

CPC classification number: H04N19/186 ,  H04N19/176 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/593 ,  H04N19/70

Abstract: Methods of palette coding to reduce the required coding process are disclosed. According to one method, smaller blocks are derived from a large block. The histogram of the large block is derived based on the histograms of smaller blocks in the large block. According to another method, one or more palette tables are derived based on multiple blocks. One palette table is used for each of the multiple blocks. According to yet another method, index map transpose is performed in the parsing stage according to the transpose flag of the index map. Accordingly, a buffer to store the transpose flags can be saved. According to still yet another method, the palette predictor update is performed using an index mapping table to avoid the need for shuffling the contents of the palette predictor stored in a palette buffer.

公开(公告)号：US09973748B1

公开(公告)日：2018-05-15

申请号：US14259144

申请日：2014-04-22

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/00 ,  H04N19/136 ,  H04N19/127 ,  H04N19/119 ,  H04N19/176 ,  H04N19/196

CPC classification number: H04N19/00139 ,  H04N19/00 ,  H04N19/00072 ,  H04N19/00103 ,  H04N19/00278 ,  H04N19/00369

Abstract: A multi-core video decoder system has a syntax parser, a storage device, a plurality of video decoder cores and a control unit. The syntax parser performs syntax parsing upon an incoming encoded video bitstream to derive required information of each picture to be decoded. The storage device buffers the required information of each picture. The control unit controls the video decoder cores to load required information of a plurality of coding rows in a picture from the storage device and then decode the coding rows in the picture, respectively.

公开(公告)号：US20180103260A1

公开(公告)日：2018-04-12

申请号：US15578184

申请日：2016-06-03

Applicant: MEDIATEK INC.

Inventor： Tzu-Der CHUANG ,  Ping CHAO ,  Ching-Yeh CHEN ,  Yu-Chen Sun ,  Chih-Ming WANG ,  Chia-Yun Cheng ,  Han-Liang Chou ,  Yu-Wen Huang

IPC: H04N19/423 ,  H04N19/51

CPC classification number: H04N19/186 ,  H04N19/176 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/593 ,  H04N19/70

Abstract: A method and apparatus of sharing an on-chip buffer or cache memory for a video coding system using coding modes including Inter prediction mode or Intra Block Copy (IntraBC) mode are disclosed. At least partial pre-deblocking reconstructed video data of a current picture is stored in an on-chip buffer or cache memory. If the current block is coded using IntraBC mode, the pre-deblocking reconstructed video data of the current picture stored in the on-chip buffer or cache memory are used to derive IntraBC prediction for the current block. In some embodiments, if the current block is coded using Inter prediction mode, Inter reference video data from the previous picture stored in the on-chip buffer or cache memory are used to derive Inter prediction for the current block. In another embodiment, the motion compensation/motion estimation unit is shared by the two modes.