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公开(公告)号:US20230024545A1
公开(公告)日:2023-01-26
申请号:US17571566
申请日:2022-01-10
Applicant: MEDIATEK INC.
Inventor: Sheng-Jen Wang , Ming-Long Wu
IPC: H04N19/423 , H04N19/176 , H04N19/119 , H04N19/129 , H04N19/70 , H04N19/124 , H04N19/60
Abstract: A video residual decoding apparatus is used for applying residual decoding to a transform block that is divided into sub-blocks, and includes a residual decoding circuit and a storage device. The residual decoding circuit enters a coefficient loop for decoding one or more syntax elements at each of coefficient positions within a sub-block that has at least one non-zero coefficient level. The coefficient loop includes one decoding pass and at least one other decoding pass. During the at least one other decoding pass, the residual decoding circuit records side information in the storage device, where the side information is indicative of specific coefficient positions at which specific syntax elements need to be decoded in the one decoding pass. During the one decoding pass, the residual decoding circuit refers to the side information for decoding the specific syntax elements at the specific coefficient positions, respectively.
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公开(公告)号:US20180020221A1
公开(公告)日:2018-01-18
申请号:US15641224
申请日:2017-07-04
Applicant: MEDIATEK INC.
Inventor: Ming-Long Wu , Tung-Hsing Wu , Li-Heng Chen , Ting-An Lin , Yi-Hsin Huang , Chung-Hua Tsai , Chia-Yun Cheng , Han-Liang Chou , Yung-Chang Chang
IPC: H04N19/13 , H04N21/2665 , H04N21/2365 , H04N21/2343 , H04N19/70 , H04N19/44 , H04N19/172 , H04N21/845 , H04N19/124
CPC classification number: H04N19/13 , H04N19/124 , H04N19/172 , H04N19/174 , H04N19/18 , H04N19/44 , H04N19/70 , H04N21/234363 , H04N21/2365 , H04N21/2665 , H04N21/8456
Abstract: A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.
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公开(公告)号:US10778980B2
公开(公告)日:2020-09-15
申请号:US16677598
申请日:2019-11-07
Applicant: MEDIATEK INC.
Inventor: Ming-Long Wu , Chia-Yun Cheng , Yung-Chang Chang
IPC: H04N19/13 , H04N19/44 , G06F9/38 , H04N19/172 , H04N19/70
Abstract: An entropy decoding apparatus includes an entropy decoding circuit, a pre-fetch circuit, and a context pre-load buffer. The pre-fetch circuit pre-fetches at least one candidate context for entropy decoding of a part of an encoded bitstream of a frame before the entropy decoding circuit starts entropy decoding of the part of the encoded bitstream of the frame. The context pre-load buffer buffers the at least one candidate context. When a target context actually needed by entropy decoding of the part of the encoded bitstream of the frame is not available in the context pre-load buffer, the context pre-load buffer instructs the pre-fetch circuit to re-fetch the target context, and the entropy decoding circuit stalls entropy decoding of the part of the encoded bitstream of the frame.
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公开(公告)号:US10123028B2
公开(公告)日:2018-11-06
申请号:US15028717
申请日:2015-09-17
Applicant: MEDIATEK INC.
Inventor: Ming-Long Wu , Chia-Yun Cheng , Yung-Chang Chang
IPC: H04N19/70 , H04N19/436 , H04N19/593 , H04N19/91 , H04N19/127 , H04N19/172 , H04N19/174 , H04N19/184 , H04N19/44
Abstract: A syntax parsing apparatus includes a plurality of syntax parsing circuits and a dispatcher. Each of the syntax parsing circuits has at least entropy decoding capability. The syntax parsing circuits generate a plurality of entropy decoding results of a plurality of image regions within a same frame, respectively. The dispatcher assigns bitstream start points of the image regions to the syntax parsing circuits, and triggers the syntax parsing circuits to start entropy decoding, respectively.
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公开(公告)号:US11765370B2
公开(公告)日:2023-09-19
申请号:US17553819
申请日:2021-12-17
Applicant: MEDIATEK INC.
Inventor: Sheng-Jen Wang , Ming-Long Wu
IPC: H04N11/02 , H04N19/44 , H04N19/176 , H04N19/119 , H04N19/105
CPC classification number: H04N19/44 , H04N19/105 , H04N19/119 , H04N19/176
Abstract: A video residual decoding apparatus includes a residual decoding circuit and a neighbor storage device. The residual decoding circuit applies residual decoding to a transform block, wherein the transform block is divided into M sub-blocks, M is a positive integer, and the M sub-blocks are processed by the residual decoding in a diagonal scan order. The neighbor storage device stores neighbor data that belong to neighboring sub-blocks and are referenced by the residual decoding of a current sub-block, wherein neighbor data belonging to a sub-block is derived from a residual decoding result of the sub-block, and a storage size of the neighbor storage device is not larger than a maximum data amount of neighbor data derived from residual decoding results of N sub-blocks, where N is a positive integer, and N is smaller than M.
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公开(公告)号:US20230059794A1
公开(公告)日:2023-02-23
申请号:US17855829
申请日:2022-07-01
Applicant: MEDIATEK INC.
Inventor: Sheng-Jen Wang , Chao-I Wu , Ming-Long Wu , Chia-Yun Cheng
IPC: H04N19/44 , H04N19/13 , H04N19/423
Abstract: A context-based adaptive binary arithmetic coding (CABAC) decoder includes a bin decode circuit and a context update circuit. The bin decode circuit supports decoding of multiple bins in one cycle. The multiple bins include a first bin and a second bin. The bin decode circuit generates a bin value of the first bin according to a first set of multiple contexts, a first range and a first offset, and generates one bin value of the second bin according to a second set of multiple contexts, a second range and a second offset. The context update circuit updates the first set of multiple contexts in response to the bin value of the first bin, to generate a first set of multiple updated contexts, and updates the second set of multiple contexts in response to said one bin value of the second bin, to generate a second set of multiple updated contexts.
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公开(公告)号:US20180020228A1
公开(公告)日:2018-01-18
申请号:US15644815
申请日:2017-07-09
Applicant: MEDIATEK INC.
Inventor: Ming-Long Wu , Chia-Yun Cheng , Yung-Chang Chang
CPC classification number: H04N19/44 , H04N19/436 , H04N19/70 , H04N19/91
Abstract: A video processing system includes a storage device, a demultiplexing circuit, and a syntax parser. The storage device includes a first buffer and a second buffer. The demultiplexing circuit performs a demultiplexing operation upon an input bitstream to write a video bitstream into the first buffer and write start points of bitstream segments of the video bitstream stored in the first buffer into the second buffer. Each start point is indicative of a start address of a corresponding bitstream segment stored in the first buffer. The syntax parser includes syntax parsing circuits and a syntax parsing control circuit. The syntax parsing control circuit fetches a start point from the second buffer, assigns the fetched start point to a syntax parsing circuit, and triggers the selected syntax parsing circuit to start syntax parsing of a bitstream segment that is read from the first buffer according to the fetched start point.
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公开(公告)号:US12143612B2
公开(公告)日:2024-11-12
申请号:US17855829
申请日:2022-07-01
Applicant: MEDIATEK INC.
Inventor: Sheng-Jen Wang , Chao-I Wu , Ming-Long Wu , Chia-Yun Cheng
IPC: H04N19/00 , H04N19/13 , H04N19/423 , H04N19/44
Abstract: A context-based adaptive binary arithmetic coding (CABAC) decoder includes a bin decode circuit and a context update circuit. The bin decode circuit supports decoding of multiple bins in one cycle. The multiple bins include a first bin and a second bin. The bin decode circuit generates a bin value of the first bin according to a first set of multiple contexts, a first range and a first offset, and generates one bin value of the second bin according to a second set of multiple contexts, a second range and a second offset. The context update circuit updates the first set of multiple contexts in response to the bin value of the first bin, to generate a first set of multiple updated contexts, and updates the second set of multiple contexts in response to said one bin value of the second bin, to generate a second set of multiple updated contexts.
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公开(公告)号:US11876990B2
公开(公告)日:2024-01-16
申请号:US17571566
申请日:2022-01-10
Applicant: MEDIATEK INC.
Inventor: Sheng-Jen Wang , Ming-Long Wu
IPC: H04N19/423 , H04N19/70 , H04N19/176 , H04N19/129 , H04N19/60 , H04N19/124 , H04N19/119
CPC classification number: H04N19/423 , H04N19/119 , H04N19/124 , H04N19/129 , H04N19/176 , H04N19/60 , H04N19/70
Abstract: A video residual decoding apparatus is used for applying residual decoding to a transform block that is divided into sub-blocks, and includes a residual decoding circuit and a storage device. The residual decoding circuit enters a coefficient loop for decoding one or more syntax elements at each of coefficient positions within a sub-block that has at least one non-zero coefficient level. The coefficient loop includes one decoding pass and at least one other decoding pass. During the at least one other decoding pass, the residual decoding circuit records side information in the storage device, where the side information is indicative of specific coefficient positions at which specific syntax elements need to be decoded in the one decoding pass. During the one decoding pass, the residual decoding circuit refers to the side information for decoding the specific syntax elements at the specific coefficient positions, respectively.
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公开(公告)号:US10412390B2
公开(公告)日:2019-09-10
申请号:US15641224
申请日:2017-07-04
Applicant: MEDIATEK INC.
Inventor: Ming-Long Wu , Tung-Hsing Wu , Li-Heng Chen , Ting-An Lin , Yi-Hsin Huang , Chung-Hua Tsai , Chia-Yun Cheng , Han-Liang Chou , Yung-Chang Chang
IPC: H04N19/13 , H04N19/70 , H04N19/44 , H04N21/23 , H04N21/84 , H04N19/124 , H04N19/172 , H04N19/18 , H04N19/174 , H04N21/2365 , H04N21/2665 , H04N21/2343 , H04N21/845
Abstract: A video encoder has a processing circuit and a universal binary entropy (UBE) syntax encoder. The processing circuit processes pixel data of a video frame to generate encoding-related data, wherein the encoding-related data comprise at least quantized transform coefficients. The UBE syntax encoder processes a plurality of syntax elements to generate UBE syntax data. The encoding-related data are represented by the syntax elements. The processing circuit operates according to a video coding standard. The video coding standard supports arithmetic encoding. The UBE syntax data contain no arithmetic-encoded syntax data.
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