公开(公告)号：US20230239068A1

公开(公告)日：2023-07-27

申请号：US17665600

申请日：2022-02-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ioannis (Giannis) Patronas ,  Wojciech Wasko ,  Paraskevas Bakopoulos ,  Dimitrios Syrivelis ,  Elad Mentovich

IPC: H04J14/08 ,  H04J14/02

CPC classification number: H04J14/08 ,  H04J14/0212 ,  H04J14/0267

Abstract: A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.

公开(公告)号：US20230236624A1

公开(公告)日：2023-07-27

申请号：US17582058

申请日：2022-01-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Natan Manevich ,  Bar Shapira

IPC: G06F1/14 ,  H04J3/06 ,  G06F1/12

CPC classification number: G06F1/14 ,  H04J3/0697 ,  H04J3/0682 ,  H04J3/0661 ,  H04J3/0679 ,  G06F1/12

Abstract: In one embodiment, a device includes a hardware clock to maintain a clock value, a hardware counter to maintain an estimation of a dynamic error bound of the clock value, and a clock controller to intermittently discipline the hardware clock responsively to a remote clock, advance the hardware counter at a rate responsively to a clock drift, and adjust the hardware counter responsively to the hardware clock being disciplined.

公开(公告)号：US20220416925A1

公开(公告)日：2022-12-29

申请号：US17359667

申请日：2021-06-28

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

IPC: H04J3/06

Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

公开(公告)号：US12289388B2

公开(公告)日：2025-04-29

申请号：US17868841

申请日：2022-07-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich

IPC: H04L7/027 ,  H04L12/40

Abstract: In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.

公开(公告)号：US20250055668A1

公开(公告)日：2025-02-13

申请号：US18448936

申请日：2023-08-13

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Arnon Sattinger ,  Wojciech Wasko ,  Maciej Machnikowski ,  Doron Fael ,  Ofir Sadeh ,  Jonathan Oliel

IPC: H04L7/033 ,  H03L7/099 ,  H04L7/10

Abstract: In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

公开(公告)号：US20240373380A1

公开(公告)日：2024-11-07

申请号：US18228505

申请日：2023-07-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Eitan Zahavi ,  Yuval Shpigelman ,  Guy Lederman ,  Liron Mula ,  Omer Shabtai

IPC: H04W56/00

Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a first control block for synchronization via a physical layer of the link, the first control block including a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating to perform a synchronization handshake. The device is further to transmit, via the link, the first control block comprising the header portion set of bits and the data portion of bit.

公开(公告)号：US20240213996A1

公开(公告)日：2024-06-27

申请号：US18101675

申请日：2023-01-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Wojciech Wasko ,  Mathias Blake ,  Dotan David Levi ,  Adam Thompson ,  Dimitris Syrivelis ,  Paraskevas Bakopoulos

IPC: H03M1/12

CPC classification number: H03M1/124

Abstract: Embodiments described herein can enable minimum processing performed at a signal device level, such that the majority of the non-domain-specific processing can be offloaded to a processing device. For example, the processing device can receive signal data from a signal device, preprocess the signal data to obtain preprocessed signal data having a data format for domain-specific processing by software executed by at least one processing unit of a processing platform, and provide the preprocessed signal data for domain-specific processing by the software executed by the at least one processing unit.

公开(公告)号：US20240204897A1

公开(公告)日：2024-06-20

申请号：US18067767

申请日：2022-12-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Natan Manevich ,  Dotan David Levi ,  Maciek Machnikowski ,  Wojciech Wasko ,  Bar Shapira ,  Jonathan Oliel ,  Ofir Sadeh

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: In one embodiment, a processing system includes an interface controller to receive a data signal from a remote link partner over a link, and recover a clock signal from the received data signal, frequency generation circuitry to receive the recovered clock signal, and output a local clock signal responsively to the received recovered clock signal, wherein the interface controller is configured to drive a transmit symbol rate responsively to the local clock signal, and a digital control loop including the interface controller and the frequency generation circuitry, wherein the interface controller is configured to identify a clock drift, generate a digital control signal responsively to the clock drift, and send the digital control signal to the frequency generation circuitry, which is configured to adjust a frequency of the local clock signal responsively to the digital control signal in order to reduce the clock drift.

公开(公告)号：US20240064443A1

公开(公告)日：2024-02-22

申请号：US17948930

申请日：2022-09-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos ,  Dotan David Levi ,  Aviv Berg ,  Wojciech Wasko ,  Dimitrios Syrivelis ,  Elad Mentovich ,  Yoav Rozenberg ,  Nikolaos Argyris

IPC: H04Q11/00

CPC classification number: H04Q11/0005 ,  H04Q11/0062 ,  H04Q2011/0007 ,  H04Q2011/0037 ,  H04Q2011/0064

Abstract: Systems, devices, and methods are described herein for reducing a link bringup time period for optical switching between network devices. An example method of the present disclosure receives an indication of a reconfiguration condition associated with an optical switch communicatively coupled to an optical communication channel and based on the reconfiguration condition, selects first data associated with a storage device or second data associated with a pattern generator device for transmission to a first network device. Selecting the first or second data may be based on a digital logic signal that indicates whether data is actively received from the second network device via the optical communication channel or may be based on a defined schedule for reconfiguring the optical switch.

公开(公告)号：US20240031121A1

公开(公告)日：2024-01-25

申请号：US17871937

申请日：2022-07-24

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Arnon Sattinger ,  Natan Manevich ,  Wojciech Wasko ,  Ariel Almog ,  Bar Or Shapira

IPC: H04L7/00

CPC classification number: H04L7/0012

Abstract: In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.