公开(公告)号：US20220197837A1

公开(公告)日：2022-06-23

申请号：US17407411

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Guanying Wu ,  Sanjay Subbarao ,  Chandra Guda

IPC: G06F13/16 ,  G06F13/37 ,  G06F9/50

Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.

公开(公告)号：US20220188009A1

公开(公告)日：2022-06-16

申请号：US17123914

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Alex J. Wesenberg ,  Johnny A. Lam ,  Michael Winterfeld

IPC: G06F3/06 ,  G06F13/28

Abstract: The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio. In one embodiment, the memory sub-system identifies a number of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects, among the block stripes, a block stripe with a highest fill ratio. The sub-system identifies, from the selected block stripe, a memory block of the LU. The sub-system performs a memory scan operation on the memory block of the memory device.

公开(公告)号：US20210200670A1

公开(公告)日：2021-07-01

申请号：US16800225

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Michael Winterfeld ,  Steven S. Williams ,  Alex J. Wesenberg ,  Johnny A. Lam

IPC: G06F12/02 ,  G06F12/0882 ,  G06F1/30 ,  G06F11/30

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.