公开(公告)号：US20240201851A1

公开(公告)日：2024-06-20

申请号：US18593165

申请日：2024-03-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Winterfeld ,  Juane Li

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0679

Abstract: A method for tracking open blocks in a memory device includes partitioning, by a memory sub-system controller, a storage region in the memory device into a plurality of channels, each channel including a plurality of planesets, and each planeset comprising a plurality of blocksets. The method further includes distributing evenly between the plurality of channels a plurality of active zones ready for a write operation. Each active zone includes one or more open blocks. The method further includes sending, by the memory sub-system controller, an open block message to a controller in the memory device, the open block message including channel identifying information, planeset identifying information, and blockset identifying information. The channel identifying information, the planeset identifying information, and the blockset identifying information collectively identify one or more open blocks ready for a write operation in the memory device.

公开(公告)号：US20240176533A1

公开(公告)日：2024-05-30

申请号：US18433688

申请日：2024-02-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Winterfeld ,  Guanying Wu

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/06

Abstract: Quad-to-single (Q2S) data structure comprising a plurality of entries maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list corresponding to a Q2S mapping entry associated with the QLC block stripe to be programmed.

公开(公告)号：US20240078033A1

公开(公告)日：2024-03-07

申请号：US18504898

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Alex J. Wesenberg ,  Johnny A. Lam ,  Michael Winterfeld

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0653 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F13/28

Abstract: The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio. In one embodiment, the memory sub-system identifies a number of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects, among the block stripes, a block stripe with a highest fill ratio. The sub-system identifies, from the selected block stripe, a memory block of the LU. The sub-system performs a memory scan operation on the memory block of the memory device.

公开(公告)号：US20220188009A1

公开(公告)日：2022-06-16

申请号：US17123914

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Alex J. Wesenberg ,  Johnny A. Lam ,  Michael Winterfeld

IPC: G06F3/06 ,  G06F13/28

Abstract: The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio. In one embodiment, the memory sub-system identifies a number of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects, among the block stripes, a block stripe with a highest fill ratio. The sub-system identifies, from the selected block stripe, a memory block of the LU. The sub-system performs a memory scan operation on the memory block of the memory device.

公开(公告)号：US20210200670A1

公开(公告)日：2021-07-01

申请号：US16800225

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Michael Winterfeld ,  Steven S. Williams ,  Alex J. Wesenberg ,  Johnny A. Lam

IPC: G06F12/02 ,  G06F12/0882 ,  G06F1/30 ,  G06F11/30

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

公开(公告)号：US11934657B2

公开(公告)日：2024-03-19

申请号：US17889179

申请日：2022-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Winterfeld ,  Juane Li

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0679

Abstract: A method for tracking open blocks in a memory device includes partitioning, by a memory sub-system controller, a storage region in the memory device into a plurality of channels, each channel including a plurality of planesets, and each planeset comprising a plurality of blocksets. The method further includes distributing evenly between the plurality of channels a plurality of active zones ready for a write operation. Each active zone includes one or more open blocks. The method further includes sending, by the memory sub-system controller, an open block message to a controller in the memory device, the open block message including channel identifying information, planeset identifying information, and blockset identifying information. The channel identifying information, the planeset identifying information, and the blockset identifying information collectively identify one or more open blocks ready for a write operation in the memory device.

公开(公告)号：US20210342267A1

公开(公告)日：2021-11-04

申请号：US17233026

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Michael Winterfeld

IPC: G06F12/0804 ,  G06F12/1009

Abstract: A system includes a non-volatile memory (NVM), and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone index; and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index for an active zone, wherein the zone write pointer includes a location in the LBA space for the active zone; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; and journal metadata of the entry of one the ZMDS or the HFUT affected by a flush transition between the ZMDS and the HFUT.

公开(公告)号：US10990526B1

公开(公告)日：2021-04-27

申请号：US15929405

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Michael Winterfeld

IPC: G06F13/00 ,  G06F12/0804 ,  G06F12/1009

Abstract: A system includes a NVM memory, and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone state and to a zone index; a journal data structure (JDS); and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index, wherein the zone write pointer includes a location in the LBA space; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; update, within the JDS, metadata of the entry of one the ZMDS or the JDS affected by a flush transition between the ZMDS and the HFUT; and in response to an asynchronous power loss event, flush the JDS and the HFUT to a NVM device.

公开(公告)号：US11934685B2

公开(公告)日：2024-03-19

申请号：US17578341

申请日：2022-01-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Winterfeld ,  Guanying Wu

IPC: G06F3/06 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/06

Abstract: A quad-to-single (Q2S) data structure comprising a plurality of the Q2S mapping entries is maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes of the non-volatile memory device with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list. The linked list corresponds to a Q2S mapping entry associated with the QLC block stripe to be programmed.

公开(公告)号：US20240062840A1

公开(公告)日：2024-02-22

申请号：US17889214

申请日：2022-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Winterfeld ,  Byron D. Harris ,  Tom Geukens ,  Juane Li ,  Fangfang Zhu

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/10

Abstract: A processing device in a memory sub-system performs a first pass of a multi-pass programming operation to coarsely program a first wordline, performs a second pass to coarsely program a second wordline adjacent to the first wordline, performs a third pass of a multi-pass programming operation to finely program the first wordline, performs a fourth pass of a multi-pass programming operation to coarsely program a third wordline adjacent to the second wordline, performs a fifth pass of a multi-pass programming operation to finely program the second wordline, and responsive to determining that at least the second wordline has been finely programmed, performs a read verify operation on one or more cells associated with the first wordline.