公开(公告)号：US20240078199A1

公开(公告)日：2024-03-07

申请号：US18506604

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Guanying Wu ,  Sanjay Subbarao ,  Chandra Guda

IPC: G06F13/16 ,  G06F9/50 ,  G06F13/37

CPC classification number: G06F13/1673 ,  G06F9/5016 ,  G06F13/161 ,  G06F13/37 ,  G06F2209/5011 ,  G06F2209/503

Abstract: A just-in-time (JIT) scheduling method includes the operations of: receiving a request to perform a memory operation using a hardware resource associated with a memory device; determining a type of the memory operation; identifying a traffic class corresponding to the memory operation; determining, based on the traffic class and the type of the memory operation, whether the memory operation is to be processed during a current scheduling time frame; and responsive to determining the memory operation is to be processed during the current scheduling time frame, submitting the memory operation to the memory device.

公开(公告)号：US11461233B2

公开(公告)日：2022-10-04

申请号：US17233026

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Michael Winterfeld

IPC: G06F12/0804 ,  G06F12/1009

Abstract: A system includes a non-volatile memory (NVM), and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone index; and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index for an active zone, wherein the zone write pointer includes a location in the LBA space for the active zone; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; and journal metadata of the entry of one the ZMDS or the HFUT affected by a flush transition between the ZMDS and the HFUT.

公开(公告)号：US20220197563A1

公开(公告)日：2022-06-23

申请号：US17407396

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Guanying Wu ,  Sanjay Subbarao ,  Chandra Guda

IPC: G06F3/06

Abstract: The memory sub-systems of the present disclosure discloses a simulator to simulate a QoS latency model for a just-in-time (JIT) scheduler. In one embodiment, a system receives a workload profile specifying a sequence of memory operations, wherein each memory operation is associated with a type of the memory operation. The system identifies a traffic class associated with each memory operation of the sequence of memory operations. The system queues each memory operation of the sequence of memory operations, based on the traffic class associated with the memory operation, in a scheduling pool of a number of scheduling pools. The system selects, based on a quality of service (QoS) policy, from the scheduling pools, one or more memory operations to be serviced within a scheduling time frame. The system determines, based on a latency profile, latency periods for each memory operation of the one or more memory operations.

公开(公告)号：US11868643B2

公开(公告)日：2024-01-09

申请号：US17123914

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Alex J. Wesenberg ,  Johnny A. Lam ,  Michael Winterfeld

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0653 ,  G06F3/064 ,  G06F3/0608 ,  G06F3/0679 ,  G06F13/28

Abstract: The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio. In one embodiment, the memory sub-system identifies a number of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects, among the block stripes, a block stripe with a highest fill ratio. The sub-system identifies, from the selected block stripe, a memory block of the LU. The sub-system performs a memory scan operation on the memory block of the memory device.

公开(公告)号：US11537512B2

公开(公告)日：2022-12-27

申请号：US17507090

申请日：2021-10-21

Applicant: Micron Technology, Inc.

Inventor： Michael Winterfeld ,  Steven S. Williams ,  Alex J. Wesenberg ,  Johnny A. Lam

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0882 ,  G06F1/30 ,  G06F11/30

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

公开(公告)号：US11194709B2

公开(公告)日：2021-12-07

申请号：US16800225

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Michael Winterfeld ,  Steven S. Williams ,  Alex J. Wesenberg ,  Johnny A. Lam

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0882 ,  G06F1/30 ,  G06F11/30

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.

公开(公告)号：US11868287B2

公开(公告)日：2024-01-09

申请号：US17407411

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Johnny A Lam ,  Alex J. Wesenberg ,  Guanying Wu ,  Sanjay Subbarao ,  Chandra Guda

IPC: G06F13/00 ,  G06F13/16 ,  G06F9/50 ,  G06F13/37

CPC classification number: G06F13/1673 ,  G06F9/5016 ,  G06F13/161 ,  G06F13/37 ,  G06F2209/503 ,  G06F2209/5011

Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.

公开(公告)号：US20210342267A1

公开(公告)日：2021-11-04

申请号：US17233026

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Michael Winterfeld

IPC: G06F12/0804 ,  G06F12/1009

Abstract: A system includes a non-volatile memory (NVM), and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone index; and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index for an active zone, wherein the zone write pointer includes a location in the LBA space for the active zone; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; and journal metadata of the entry of one the ZMDS or the HFUT affected by a flush transition between the ZMDS and the HFUT.

公开(公告)号：US10990526B1

公开(公告)日：2021-04-27

申请号：US15929405

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Johnny A. Lam ,  Alex J. Wesenberg ,  Michael Winterfeld

IPC: G06F13/00 ,  G06F12/0804 ,  G06F12/1009

Abstract: A system includes a NVM memory, and a volatile memory to store: a zone map data structure (ZMDS) that maps a zone of a logical block address (LBA) space to a zone state and to a zone index; a journal data structure (JDS); and a high frequency update table (HFUT). A processing device is to: write, within an entry of the HFUT, a value of a zone write pointer corresponding to the zone index, wherein the zone write pointer includes a location in the LBA space; write, within an entry of the ZMDS, a table index value that points to the entry of the HFUT; update, within the JDS, metadata of the entry of one the ZMDS or the JDS affected by a flush transition between the ZMDS and the HFUT; and in response to an asynchronous power loss event, flush the JDS and the HFUT to a NVM device.

公开(公告)号：US20240078033A1

公开(公告)日：2024-03-07

申请号：US18504898

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Alex J. Wesenberg ,  Johnny A. Lam ,  Michael Winterfeld

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0653 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F13/28

Abstract: The memory sub-systems of the present disclosure selects, for memory scans, a memory block which has a highest page fill ratio. In one embodiment, the memory sub-system identifies a number of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects, among the block stripes, a block stripe with a highest fill ratio. The sub-system identifies, from the selected block stripe, a memory block of the LU. The sub-system performs a memory scan operation on the memory block of the memory device.