公开(公告)号：US20250125294A1

公开(公告)日：2025-04-17

申请号：US19000041

申请日：2024-12-23

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L23/00

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

公开(公告)号：US11804467B2

公开(公告)日：2023-10-31

申请号：US16912547

申请日：2020-06-25

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: B23K1/005 ,  H01L23/00 ,  B23K1/00 ,  B23K101/40

CPC classification number: H01L24/75 ,  B23K1/005 ,  B23K1/0016 ,  H01L24/17 ,  H01L24/81 ,  B23K2101/40 ,  H01L2224/17181 ,  H01L2224/75272 ,  H01L2224/75301 ,  H01L2224/8121 ,  H01L2224/81203

Abstract: A radiative heat collective bonder or gangbonder for packaging a semiconductor die stack is provided. The bonder generally includes a shroud positioned at least partially around the die stack and a radiative heat source positioned inward of the shroud and configured to emit a radiative heat flux in a direction away from the shroud. The bonder may further include a bondhead configured to contact the backside of the topmost die in the die stack and optionally include another bondhead configured to contact a substrate beneath the die stack. The radiative heat source may be configured to direct the radiative heat flux to at least a portion of the die stack to reduce a vertical temperature gradient in the die stack. One or both of the bondheads may be configured to concurrently direct a conductive heat flux into the die stack.

公开(公告)号：US20210407944A1

公开(公告)日：2021-12-30

申请号：US16916325

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Chao Wen Wang

IPC: H01L23/00

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

公开(公告)号：US11056443B2

公开(公告)日：2021-07-06

申请号：US16554986

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Chao Wen Wang

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L25/065 ,  H01L21/74 ,  H01L21/56 ,  H01L21/48 ,  H01L23/492

Abstract: An apparatus comprises conductive segments comprising an uneven topography comprising upper surfaces of the conductive segments protruding above an upper surface of underlying materials, a first passivation material substantially conformally overlying the conductive segments, and a second passivation material overlying the first passivation material. The second passivation material is relatively thicker than the first passivation material. The apparatus also comprises structural elements overlying the second passivation material. The second passivation material has a thickness sufficient to provide a substantially flat surface above the uneven topography of the underlying conductive segments at least in regions supporting the structural elements. Microelectronic devices, memory devices, and related methods are also disclosed.