公开(公告)号：US11250903B2

公开(公告)日：2022-02-15

申请号：US16811738

申请日：2020-03-06

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Chikara Kondo ,  Daigo Toyama

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/406

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.

公开(公告)号：US11537306B2

公开(公告)日：2022-12-27

申请号：US17200421

申请日：2021-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Daigo Toyama

IPC: G06F3/06 ,  G06F12/123

Abstract: A cold data detector circuit includes a bubble break register that is configured to detect cold data in a memory system including main memory and secondary memory. The bubble break register selectively shifts received segment addresses to fill empty slots without having to wait until the empty slots are shifted out an end slot, and may provide an indication of cold data in response to every slot of the register being filled with a different respective segment address.

公开(公告)号：US20220108995A1

公开(公告)日：2022-04-07

申请号：US17063194

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Daigo Toyama

IPC: H01L27/112 ,  G11C17/16 ,  G11C11/419

Abstract: Apparatuses, methods, and computing systems relating to three-dimensional fuse architectures are disclosed. An apparatus includes a semiconductor substrate, a fuse array on or in the semiconductor substrate, and fuse circuitry on or in the semiconductor substrate. The fuse array includes fuse cells. The fuse circuitry is configured to access the fuse cells. The fuse circuitry is offset from the fuse array such that the fuse circuitry is disposed between the semiconductor substrate and the fuse array, or the fuse array is disposed between the semiconductor substrate and the fuse circuitry.

公开(公告)号：US11270758B2

公开(公告)日：2022-03-08

申请号：US16942503

申请日：2020-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Yoshihito Morishita ,  Daigo Toyama ,  Takamasa Suzuki

IPC: G11C7/00 ,  G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

公开(公告)号：US20200211617A1

公开(公告)日：2020-07-02

申请号：US16811738

申请日：2020-03-06

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Chikara Kondo ,  Daigo Toyama

IPC: G11C11/4074 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/14

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.

公开(公告)号：US20200066324A1

公开(公告)日：2020-02-27

申请号：US16107998

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Chikara Kondo ,  Daigo Toyama

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.