公开(公告)号：US20220335995A1

公开(公告)日：2022-10-20

申请号：US17810520

申请日：2022-07-01

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Daigo Toyama

IPC: G11C7/22 ,  G11C7/10

Abstract: An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory array access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.

公开(公告)号：US20220036939A1

公开(公告)日：2022-02-03

申请号：US16942503

申请日：2020-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Yoshihito Morishita ,  Daigo Toyama ,  Takamasa Suzuki

IPC: G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

公开(公告)号：US11551746B2

公开(公告)日：2023-01-10

申请号：US16953214

申请日：2020-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Daigo Toyama ,  Chikara Kondo ,  Takehiro Hasegawa

IPC: G11C7/12 ,  G11C11/4097 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F3/06

Abstract: Apparatuses, systems, and methods for faster memory access regions. A memory array may have a first bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

公开(公告)号：US20220157372A1

公开(公告)日：2022-05-19

申请号：US16953214

申请日：2020-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Daigo Toyama ,  Chikara Kondo ,  Takehiro Hasegawa

IPC: G11C11/4097 ,  G11C11/4091

Abstract: Apparatuses, systems, and methods for faster memory access regions. A memory array may have a fiat bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

公开(公告)号：US20220157367A1

公开(公告)日：2022-05-19

申请号：US17590710

申请日：2022-02-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Yoshihito Morishita ,  Daigo Toyama ,  Takamasa Suzuki

IPC: G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

公开(公告)号：US11651815B2

公开(公告)日：2023-05-16

申请号：US17590710

申请日：2022-02-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Yoshihito Morishita ,  Daigo Toyama ,  Takamasa Suzuki

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4087 ,  G11C11/40615

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

公开(公告)号：US11380376B2

公开(公告)日：2022-07-05

申请号：US17003913

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Daigo Toyama

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

Abstract: An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory army access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.

公开(公告)号：US20220068329A1

公开(公告)日：2022-03-03

申请号：US17003913

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Daigo Toyama

IPC: G11C7/22 ,  G11C7/10

Abstract: An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory army access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.

公开(公告)号：US11502089B2

公开(公告)日：2022-11-15

申请号：US17063194

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Daigo Toyama

IPC: G11C17/16 ,  H01L27/112 ,  G11C11/419

Abstract: Apparatuses, methods, and computing systems relating to three-dimensional fuse architectures are disclosed. An apparatus includes a semiconductor substrate, a fuse array on or in the semiconductor substrate, and fuse circuitry on or in the semiconductor substrate. The fuse array includes fuse cells. The fuse circuitry is configured to access the fuse cells. The fuse circuitry is offset from the fuse array such that the fuse circuitry is disposed between the semiconductor substrate and the fuse array, or the fuse array is disposed between the semiconductor substrate and the fuse circuitry.

公开(公告)号：US20220291853A1

公开(公告)日：2022-09-15

申请号：US17200421

申请日：2021-03-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Daigo Toyama

IPC: G06F3/06

Abstract: A cold data detector circuit includes a bubble break register that is configured to detect cold data in a memory system including main memory and secondary memory. The bubble break register selectively shifts received segment addresses to fill empty slots without having to wait until the empty slots are shifted out an end slot, and may provide an indication of cold data in response to every slot of the register being filled with a different respective segment address.