公开(公告)号：US20240186267A1

公开(公告)日：2024-06-06

申请号：US18442498

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L23/562 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US20210391352A1

公开(公告)日：2021-12-16

申请号：US16902897

申请日：2020-06-16

Applicant: Micron Technology, Inc

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunal Shrotri ,  Swapnil Lengade

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11127691B2

公开(公告)日：2021-09-21

申请号：US16235665

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.