公开(公告)号：US12004346B2

公开(公告)日：2024-06-04

申请号：US17200169

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Swapnil Lengade ,  Jeremy Adams ,  Naiming Liu ,  Jeslin J. Wu ,  Kadir Abdul ,  Carlo Mendoza Orofeo

IPC: H10B43/27 ,  H01L21/02 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02274 ,  H10B41/27

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20220238553A1

公开(公告)日：2022-07-28

申请号：US17718863

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunai Shrotri ,  Swapnil Lengade

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3115

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200211981A1

公开(公告)日：2020-07-02

申请号：US16235665

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US20250157950A1

公开(公告)日：2025-05-15

申请号：US19025955

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US20230292510A1

公开(公告)日：2023-09-14

申请号：US18198752

申请日：2023-05-17

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunal Shrotri ,  Swapnil Lengade

IPC: H10B43/27 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3115 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/31111 ,  H01L21/3115 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11706924B2

公开(公告)日：2023-07-18

申请号：US17718863

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunal Shrotri ,  Swapnil Lengade

IPC: H10B43/27 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3115 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/022 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/3115 ,  H01L21/31111 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11916024B2

公开(公告)日：2024-02-27

申请号：US17447618

申请日：2021-09-14

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L23/562 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76224

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US11329064B2

公开(公告)日：2022-05-10

申请号：US16902897

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunal Shrotri ,  Swapnil Lengade

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210407930A1

公开(公告)日：2021-12-30

申请号：US17447618

申请日：2021-09-14

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Adam L. Olson ,  John D. Hopkins ,  Jeslin J. Wu

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

公开(公告)号：US20240215246A1

公开(公告)日：2024-06-27

申请号：US18596580

申请日：2024-03-05

Applicant: Micron Technology, Inc.

Inventor： Swapnil A. Lengade ,  Jeremy Adams ,  Naiming Liu ,  Jeslin J. Wu ,  Kadir Abdul ,  Carlo Mendoza Orofeo

IPC: H10B43/27 ,  H01L21/02 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02274 ,  H10B41/27

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising a vertically alternating sequence of insulative structures and additional insulative structures, at least some of the additional insulative structures comprising silicon nitride having a ratio of nitrogen atoms to silicon atoms greater than about 1.58:1.00, forming openings through the stack structure, and forming cell pillar structures within the openings, the cell pillar structures individually comprising a semiconductor channel material vertically extending through the stack structure. Related methods, microelectronic devices, memory devices, and electronic systems are also described.