公开(公告)号：US11700729B2

公开(公告)日：2023-07-11

申请号：US17524913

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.

公开(公告)号：US11329064B2

公开(公告)日：2022-05-10

申请号：US16902897

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunal Shrotri ,  Swapnil Lengade

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11075219B2

公开(公告)日：2021-07-27

申请号：US16545375

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/11519

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US20210057433A1

公开(公告)日：2021-02-25

申请号：US16545375

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US11626423B2

公开(公告)日：2023-04-11

申请号：US17373278

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H01L21/311 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US20220238553A1

公开(公告)日：2022-07-28

申请号：US17718863

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Ramey M. Abdelrahaman ,  Jeslin J. Wu ,  Chandra Tiwari ,  Kunai Shrotri ,  Swapnil Lengade

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3115

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210217761A1

公开(公告)日：2021-07-15

申请号：US16739581

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Chandra Tiwari

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/06 ,  G11C5/02

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. A horizontal pattern of operative memory-cell pillars extends through the insulative tiers and the conductive tiers in individual of the memory blocks. The operative memory-cell pillars have intrinsic compressive mechanical stress. At least one dummy structure in the individual memory blocks extends through at least upper of the insulative tiers and the conductive tiers. The at least one dummy structure is at least one of (a) and (b), where (a): at a lateral edge of the horizontal pattern, and (b): at a longitudinal end of the horizontal pattern. The at least one dummy structure has intrinsic tensile mechanical stress. Other embodiments, including methods, are disclosed.

公开(公告)号：US20240071932A1

公开(公告)日：2024-02-29

申请号：US17944343

申请日：2022-09-14

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Chandra Tiwari

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. The first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. An insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. Individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. The insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. Insulative material is formed in the cavity directly above the insulating lining. Conductive vias are formed through the insulative material and the insulating lining. Individual of the conductive vias are directly above and directly against the conducting material of the tread of individual of the stairs. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230209827A1

公开(公告)日：2023-06-29

申请号：US18116946

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H10B43/27 ,  H01L21/311 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/31111 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US11205654B2

公开(公告)日：2021-12-21

申请号：US16550238

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Ramey M. Abdelrahaman ,  Narula Bilik ,  Daniel Billingsley ,  Zhenyu Bo ,  Joan M. Kash ,  Matthew J. King ,  Andrew Li ,  David Neumeyer ,  Wei Yeeng Ng ,  Yung K. Pak ,  Chandra Tiwari ,  Yiping Wang ,  Lance Williamson ,  Xiaosong Zhang

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.