公开(公告)号：US20230343407A1

公开(公告)日：2023-10-26

申请号：US17725025

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G11C29/36 ,  G11C29/46 ,  G11C29/12 ,  G11C29/56 ,  G11C29/18

CPC classification number: G11C29/36 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/46 ,  G11C29/56 ,  G11C2029/3602 ,  G11C2029/5602

Abstract: Systems and methods for filtering data (DQ) signals are described herein. The systems and methods may involve operating a memory to enter a training mode and sending a command to a decoder while the memory is in the training mode. The decoder may generate a command/address waveform in response to the command. The systems and methods may involve transmitting a burst indicator waveform via a first pin of the memory. The burst indicator waveform may be generated by a burst indicator generator of the memory based on the command/address waveform.

公开(公告)号：US20230409708A1

公开(公告)日：2023-12-21

申请号：US17843291

申请日：2022-06-17

Applicant: Micron Technology, Inc.

Inventor： Kai Wang ,  Minjian Wu

IPC: G06F21/56 ,  G06F3/06

CPC classification number: G06F21/56 ,  G06F3/0632 ,  G06F2221/034 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/0659

Abstract: A system to progressively generate responses configured to mitigate risk associated with row hammer attacks. Between two successive refreshing of memory cells in a memory device, increasing thresholds are used to detect row hammer attacks. For example, after a first alert of row hammer attacks is generated using a first lower threshold, a first operation associated with the first lower threshold is initiated to mitigate risk associated with row hammer attack; and a second higher threshold is used to detect row hammer attacks. After a second alert of row hammer attacks is generated using the second lower threshold, a second operation associated with the second lower threshold is initiated to mitigate risk associated with row hammer attack.

公开(公告)号：US20230043306A1

公开(公告)日：2023-02-09

申请号：US17877210

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Kai Wang

IPC: G11C11/406 ,  G11C29/52

Abstract: Methods, systems, and devices for techniques for memory error correction are described. A memory system may support a refresh with error correction code (ECC) operation. The refresh with ECC operation may be indicated in a command from a host device to a memory device, or the memory device may support executing the refresh with ECC operation autonomously, for example as part of a self-refresh operation. The refresh with ECC operation may cause the memory system to, as part of a refresh operation for a row of a memory array, perform an error correction operation on at least a portion of the row. The error correction operation may correct bit errors in a set of data before an additional bit of the set of data is corrupted. The address of the portion of the row may be determined using one or more counters associated with an ECC patrol block.