公开(公告)号：US20170337953A1

公开(公告)日：2017-11-23

申请号：US15669300

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C8/12 ,  G06F3/06 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US20170285988A1

公开(公告)日：2017-10-05

申请号：US15090301

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G06F3/06

CPC classification number: G11C7/1006 ,  G06F12/06 ,  G06F13/1668 ,  G06F2212/1028 ,  G11C7/1015 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2209 ,  Y02D10/13

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.