公开(公告)号：US10522199B2

公开(公告)日：2019-12-31

申请号：US15669300

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C7/06 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US20230043636A1

公开(公告)日：2023-02-09

申请号：US17971300

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/408 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US10453502B2

公开(公告)日：2019-10-22

申请号：US15090301

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G11C7/10 ,  G11C11/4074 ,  G11C8/12 ,  G06F12/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a power budget operation associated with the memory operation to be performed, based at least in part on information stored in a budget area, such as a register. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation, or incremented upon completion of an operation, associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory (PIM) operation.

公开(公告)号：US20210390988A1

公开(公告)日：2021-12-16

申请号：US17461084

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4074 ,  G06F12/06 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

公开(公告)号：US20210217449A1

公开(公告)日：2021-07-15

申请号：US17215581

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/408 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US11557326B2

公开(公告)日：2023-01-17

申请号：US17461084

申请日：2021-08-30

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G11C11/4074 ,  G11C7/10 ,  G11C11/4076 ,  G06F12/06 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

公开(公告)号：US11482260B2

公开(公告)日：2022-10-25

申请号：US17215581

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G06F3/06 ,  G11C8/12 ,  G11C7/06

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US11107510B2

公开(公告)日：2021-08-31

申请号：US16657445

申请日：2019-10-18

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G11C8/12 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4074 ,  G06F12/06 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a budget area, such as a register, to perform a power budget operation associated with the memory operation. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation or incremented upon completion of an operation associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory operation.

公开(公告)号：US10964358B2

公开(公告)日：2021-03-30

申请号：US16536941

申请日：2019-08-09

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C11/4096 ,  G11C11/4091 ,  G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G11C7/06 ,  G11C11/408

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US20200051599A1

公开(公告)日：2020-02-13

申请号：US16657445

申请日：2019-10-18

Applicant: Micron Technology, Inc.

Inventor： Kelley D. Dobelstein ,  Jason T. Zawodny ,  Kyle B. Wheeler

IPC: G11C7/10 ,  G11C11/4076 ,  G11C11/4074 ,  G06F12/06 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4096 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.