公开(公告)号：US12300300B2

公开(公告)日：2025-05-13

申请号：US17660199

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4076

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

公开(公告)号：US20250046359A1

公开(公告)日：2025-02-06

申请号：US18742634

申请日：2024-06-13

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Donald Morgan

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses and techniques for controlling usage-based disturbance mitigation are described. In an example aspect, usage-based disturbance mitigation is performed between activation and precharging of a row. More specifically, usage-based disturbance circuitry performs an array counter update procedure while the row is active. The techniques for controlling usage-based disturbance mitigation control timing of the array counter update procedure at a multi-bank level or a local-bank level. Additionally, the techniques for controlling usage-based disturbance mitigation control a timing of a precharging operation to ensure completion of the array counter update procedure. The techniques for controlling usage-based disturbance mitigation are not limited to the array counter update procedure and can generally be applied to other aspects of usage-based disturbance mitigation, such as bit-error detection and/or correction.

公开(公告)号：US20230343380A1

公开(公告)日：2023-10-26

申请号：US17660201

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4085

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include a controller with logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

公开(公告)号：US20230342048A1

公开(公告)日：2023-10-26

申请号：US17660195

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US20230342047A1

公开(公告)日：2023-10-26

申请号：US17660192

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.