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公开(公告)号：US20210304813A1
公开(公告)日：2021-09-30
申请号：US17347957
申请日：2021-06-15
Applicant: Micron Technology, Inc.
Inventor： Timothy B. Cowles , Jiyun Li , Beau D. Barry , Matthew D. Jenkinson , Nathaniel J. Meier , Michael A. Shore , Adam J. Grenzebach , Dennis G. Montierth
IPC: G11C11/406 , G11C11/408
Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
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公开(公告)号：US11069393B2
公开(公告)日：2021-07-20
申请号：US16431641
申请日：2019-06-04
Applicant: Micron Technology, Inc.
Inventor： Timothy B. Cowles , Jiyun Li , Beau D. Barry , Matthew D. Jenkinson , Nathaniel J. Meier , Michael A. Shore , Adam J. Grenzebach , Dennis G. Montierth
IPC: G11C7/00 , G11C11/406 , G11C11/408
Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
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公开(公告)号：US10964374B2
公开(公告)日：2021-03-30
申请号：US16549411
申请日：2019-08-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Matthew D. Jenkinson , Nathaniel J. Meier , Dennis G. Montierth
IPC: G11C7/00 , G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
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公开(公告)号：US20210057013A1
公开(公告)日：2021-02-25
申请号：US16549942
申请日：2019-08-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Matthew D. Jenkinson , Jiyun Li , Dennis G. Montierth , Nathaniel J. Meier
IPC: G11C11/408 , G06F12/0802 , H03K3/03 , G11C8/16
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a lust direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).
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公开(公告)号：US20250061020A1
公开(公告)日：2025-02-20
申请号：US18778645
申请日：2024-07-19
Applicant: Micron Technology, Inc.
Abstract: Apparatuses, systems, and methods for tracking latch upset events using a trim register are described. An example method includes reading trim data from trim registers in a non-volatile memory device. The example method can further include generating parity data for the trim data. The example method can further include storing the parity data in the trim registers. The example method can further include, subsequent to the generation and storage of the parity data, re-reading the trim data from the trim registers, generating additional parity data, and comparing the parity data to the additional parity data.
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Patent Agency Ranking
公开(公告)号：US11948655B2
公开(公告)日：2024-04-02
申请号：US17726139
申请日：2022-04-21
Applicant: Micron Technology, Inc.
CPC classification number: G11C29/4401 , G11C29/18 , G11C29/787 , H03K19/20 , G11C2029/4402
Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
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公开(公告)号：US20230343409A1
公开(公告)日：2023-10-26
申请号：US17726139
申请日：2022-04-21
Applicant: Micron Technology, Inc.
CPC classification number: G11C29/4401 , G11C29/18 , G11C29/787 , H03K19/20 , G11C2029/4402
Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
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公开(公告)号：US20230222032A1
公开(公告)日：2023-07-13
申请号：US17572129
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Jenkinson , Seth A. Eichmeyer , Christopher G. Wieduwilt
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/0793 , G06F11/3037
Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.
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公开(公告)号：US11417383B2
公开(公告)日：2022-08-16
申请号：US17186913
申请日：2021-02-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Matthew D. Jenkinson , Nathaniel J. Meier , Dennis G. Montierth
IPC: G11C7/00 , G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
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公开(公告)号：US11302374B2
公开(公告)日：2022-04-12
申请号：US16549411
申请日：2019-08-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Matthew D. Jenkinson , Nathaniel J. Meier , Dennis G. Montierth
IPC: G11C7/00 , G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
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