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1.发明申请公开(公告)号：US20210082529A1
公开(公告)日：2021-03-18
申请号：US17107235
申请日：2020-11-30
IPC分类号： G11C16/34 , G11C11/406
摘要： Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
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2.发明申请公开(公告)号：US20200273518A1
公开(公告)日：2020-08-27
申请号：US15930268
申请日：2020-05-12
IPC分类号： G11C11/406 , G11C11/00 , G11C13/00 , G11C11/22 , G11C11/16
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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3.发明申请公开(公告)号：US20200143872A1
公开(公告)日：2020-05-07
申请号：US16734241
申请日：2020-01-03
IPC分类号： G11C11/406 , G11C11/16 , G11C13/00 , G11C11/22 , G11C11/00
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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4.发明申请公开(公告)号：US20190325966A1
公开(公告)日：2019-10-24
申请号：US15959868
申请日：2018-04-23
IPC分类号： G11C16/14 , G11C16/08 , G11C17/16 , G11C17/18 , G11C16/22 , G11C13/00 , G11C11/16 , G11C11/22 , G11C16/30
摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.
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5.发明申请公开(公告)号：US20190295666A1
公开(公告)日：2019-09-26
申请号：US15933678
申请日：2018-03-23
IPC分类号： G11C16/34 , G11C11/406
摘要： Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.
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6.发明申请公开(公告)号：US20190228816A1
公开(公告)日：2019-07-25
申请号：US16375073
申请日：2019-04-04
IPC分类号： G11C11/406
CPC分类号： G11C11/40618 , G11C11/005 , G11C11/1675 , G11C11/2275 , G11C13/0033 , G11C13/0069
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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7.发明授权公开(公告)号：US10297309B1
公开(公告)日：2019-05-21
申请号：US16015441
申请日：2018-06-22
IPC分类号： G11C7/00 , G11C11/406
摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
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公开(公告)号：US20180082719A1
公开(公告)日：2018-03-22
申请号：US15823013
申请日：2017-11-27
CPC分类号： G11C7/065 , G11C5/06 , G11C7/06 , G11C7/08 , G11C7/1006 , G11C7/1036 , G11C7/22 , G11C8/10 , G11C11/4091 , G11C19/00 , G11C2207/002 , G11C2207/005
摘要： The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array.
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9.发明申请APPARATUSES AND METHODS FOR COMPRESSING DATA RECEIVED OVER MULTIPLE MEMORY ACCESSES 有权用于压缩通过多个存储器访问接收的数据的装置和方法公开(公告)号：US20140237305A1
公开(公告)日：2014-08-21
申请号：US13771838
申请日：2013-02-20
IPC分类号： G06F11/07
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/3187 , G01R31/3193 , G01R31/31932 , G01R31/31935 , G06F11/076 , G11C29/44 , G11C29/48 , G11C29/70 , G11C2029/4002 , G11C2029/5606
摘要： Apparatuses and methods for compressing data responsive to a plurality of memory accesses is described. An example compression circuit includes a comparator configured to compare data provided by a group of memory cells associated with a repair address. Each subset of one or more bits of the data is sequentially provided by the group of memory cells responsive to a respective memory access of a plurality of memory accesses. The example compression circuit further including an error bit latch coupled to the comparison circuit. The error bit latch configured to, responsive to an output received from the comparison circuit indicating an error, compress the data to an error bit by setting the error bit to an error detected state and latching the error bit having the error detected state.
摘要翻译： 描述了响应于多个存储器访问来压缩数据的装置和方法。 示例压缩电路包括比较器，其被配置为比较由与修复地址相关联的一组存储器单元提供的数据。 响应于多个存储器访问的相应存储器访问，由该组存储器单元顺序地提供数据的一个或多个位的每个子集。 示例压缩电路还包括耦合到比较电路的错误位锁存器。 错误位锁存器被配置为响应于从比较电路接收的指示错误的输出，通过将错误位设置为错误检测状态并锁存具有错误检测状态的错误位来将数据压缩到错误位。
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公开(公告)号：US11158364B2
公开(公告)日：2021-10-26
申请号：US16428625
申请日：2019-05-31
IPC分类号： G11C7/00 , G11C11/406 , G11C11/408
摘要： The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.
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