公开(公告)号：US12080336B2

公开(公告)日：2024-09-03

申请号：US17662198

申请日：2022-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jiyun Li ,  Christopher J. Kawamura ,  Tae H. Kim

IPC: G11C11/4091 ,  H03F3/45

CPC classification number: G11C11/4091 ,  H03F3/45264

Abstract: Apparatuses, systems, and methods for compensated sense amplifier with cross-coupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.

公开(公告)号：US20220384448A1

公开(公告)日：2022-12-01

申请号：US17876461

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Scott J. Derner

IPC: H01L27/108 ,  H01L23/522 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4074

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

公开(公告)号：US11437381B2

公开(公告)日：2022-09-06

申请号：US16785942

申请日：2020-02-10

Applicant: Micron Technology, inc.

Inventor： Jiyun Li ,  Scott J. Derner

IPC: H01L27/108 ,  H01L23/522 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4074

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

公开(公告)号：US11423972B2

公开(公告)日：2022-08-23

申请号：US17021221

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Yuan He

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4091

Abstract: Some embodiments include an integrated assembly having a memory deck over a base, and having an array of memory cells along the memory deck. The array includes rows which extend along a row direction and columns which extend along a column direction. Wordlines are along the rows and digit-lines are along the columns. CONTROL circuitry is along the base and includes WORDLINE DRIVER circuitry coupled with the wordlines. The CONTROL circuitry is subdivided amongst banks. The banks are elongated along the row direction. Each of the banks is subdivided amongst a series of sections, with the sections being arranged in section rows which extend along the row direction. Each of the sections includes a series of patches, with the patches including INPUT/OUTPUT circuitry. The patches are arranged in groups, with the groups sharing portions of the WORDLINE DRIVER circuitry.

公开(公告)号：US20220084578A1

公开(公告)日：2022-03-17

申请号：US17021221

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Yuan He

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4093

Abstract: Some embodiments include an integrated assembly having a memory deck over a base, and having an array of memory cells along the memory deck. The array includes rows which extend along a row direction and columns which extend along a column direction. Wordlines are along the rows and digit-lines are along the columns. CONTROL circuitry is along the base and includes WORDLINE DRIVER circuitry coupled with the wordlines. The CONTROL circuitry is subdivided amongst banks. The banks are elongated along the row direction. Each of the banks is subdivided amongst a series of sections, with the sections being arranged in section rows which extend along the row direction. Each of the sections includes a series of patches, with the patches including INPUT/OUTPUT circuitry. The patches are arranged in groups, with the groups sharing portions of the WORDLINE DRIVER circuitry.

公开(公告)号：US20200381040A1

公开(公告)日：2020-12-03

申请号：US16428625

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US20240413841A1

公开(公告)日：2024-12-12

申请号：US18738499

申请日：2024-06-10

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Toby D. Robbs

IPC: H03M13/11 ,  H03M13/00

Abstract: Apparatuses and methods for on-device error correction implemented in a memory. A memory may have a first column plane comprising a first number of bit lines and a parity column plane that has a second number of parity bit lines in which the first number is different than the second number. In an access operation, a column select signal may activate the first number of bit lines in the first column plane and the second number of parity bit lines in the second column plane.

公开(公告)号：US12051460B2

公开(公告)日：2024-07-30

申请号：US17447490

申请日：2021-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tae H. Kim ,  Christopher J. Kawamura ,  Jiyun Li

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/12 ,  G11C11/4074 ,  G11C2207/002 ,  G11C2207/005

Abstract: Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.

公开(公告)号：US20230395101A1

公开(公告)日：2023-12-07

申请号：US17805090

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Yuan He

IPC: G11C7/08 ,  G11C7/14 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/14 ,  G11C7/1096 ,  G11C7/1069

Abstract: Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.

公开(公告)号：US20230360690A1

公开(公告)日：2023-11-09

申请号：US17662198

申请日：2022-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jiyun Li ,  Christopher J. Kawamura ,  Tae H. Kim

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  H03F3/45264

Abstract: Apparatuses, systems, and methods for compensated sense amplifier with crosscoupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.