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公开(公告)号：US20190278363A1
公开(公告)日：2019-09-12
申请号：US15919053
申请日：2018-03-12
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
IPC: G06F1/32 , G06F12/02 , G11C16/26 , G11C16/30 , G11C7/20 , G11C7/22 , H01L27/11521 , H01L27/11526
Abstract: A power management integrated circuit (PMIC) that has multiple sets of circuits to provide certain same power management functionalities in different power modes, such as voltage, current and temperature sensing and/or measuring, generating of reference states or biases to effectuate circuit protection in various conditions, such as under voltages, over voltages, etc. One set of circuits is configured to operate during a normal mode and is optimized for performance, speed and/or accuracy. Another set of circuits is configured to operate during a sleep mode and is optimized for reduced power consumption where the performance, speed and/or accuracy may be inferior to the circuits for the normal mode but the functionality is maintained within the low power consumption constraint.
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公开(公告)号：US10325631B1
公开(公告)日：2019-06-18
申请号：US15918627
申请日：2018-03-12
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
Abstract: A power management integrated circuit (PMIC) receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the PMIC generates an interrupt signal causing the memory system to shut down safely without data loss.
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公开(公告)号：US20230068931A1
公开(公告)日：2023-03-02
申请号：US18054770
申请日：2022-11-11
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
Abstract: A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.
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公开(公告)号：US11552552B2
公开(公告)日：2023-01-10
申请号：US15918960
申请日：2018-03-12
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
Abstract: A memory system having a non-volatile memory and a power management integrated circuit (PMIC) that has a voltage regulator to apply a voltage on the non-volatile memory during normal operations. During a shutdown process, the PMIC has a bleeder that is activated to reduce the voltage applied on the non-volatile memory to a level that is below a programmable threshold, before allowing the memory system to restart again. During the bleeding operation, a comparator of the PMIC compares the voltage applied to the non-volatile memory and the threshold to determine whether the shutdown process can be terminated for a restart.
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公开(公告)号：US11379032B2
公开(公告)日：2022-07-05
申请号：US17099158
申请日：2020-11-16
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
IPC: G06F1/3296 , G06F12/02 , G11C16/26 , G11C16/30 , H01L27/11526 , G11C7/20 , G11C7/22 , H01L27/11521 , G11C5/14
Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.
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Patent Agency Ranking
公开(公告)号：US11024345B2
公开(公告)日：2021-06-01
申请号：US17001548
申请日：2020-08-24
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
IPC: G11C5/14 , G11C11/4074 , G06F1/28 , G06F1/30 , H03K17/687
Abstract: Disclosed is an improved load switch driver for Power Management Integrated Circuit (PMIC) devices. In one embodiment, a PMIC is disclosed comprising a gate driver, the gate driver connected to the gate of a switch; an operation frequency generator connected to the gate driver and configured to supply a periodic voltage to the gate driver; and a voltage sensor, the voltage sensor connected to the operation frequency generator and the source of the switch, the voltage sensor configured to monitor a drain-source voltage of the switch and lower the frequency of the operation frequency generator to a second frequency in response to detecting a collapse of the drain-source voltage.
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公开(公告)号：US20210089115A1
公开(公告)日：2021-03-25
申请号：US17099158
申请日：2020-11-16
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
IPC: G06F1/3296 , G06F12/02 , G11C16/26 , G11C16/30 , H01L27/11526 , G11C7/20 , G11C7/22 , H01L27/11521 , G11C5/14
Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.
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公开(公告)号：US10942657B2
公开(公告)日：2021-03-09
申请号：US15919102
申请日：2018-03-12
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
IPC: G06F1/32 , G06F3/06 , G06F1/3246 , G06F1/3225 , G06F11/34
Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.
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公开(公告)号：US10852812B2
公开(公告)日：2020-12-01
申请号：US16395974
申请日：2019-04-26
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
IPC: G06F1/3296 , G06F12/02 , G11C16/26 , G11C16/30 , H01L27/11526 , G11C7/20 , G11C7/22 , H01L27/11521 , G11C5/14
Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.
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公开(公告)号：US10783934B2
公开(公告)日：2020-09-22
申请号：US16676846
申请日：2019-11-07
Applicant: Micron Technology, Inc.
Inventor： Matthew David Rowley
Abstract: A power management circuit receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the circuit generates an interrupt signal causing the memory system to shut down safely without data loss.
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