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11.发明公开公开(公告)号：US20240160577A1
公开(公告)日：2024-05-16
申请号：US18505302
申请日：2023-11-09
Applicant: Micron Technology, Inc.
Inventor： Raja V. S. Halaharivi , Prateek Sharma , Sumangal Chakrabarty , Venkat R. Gaddam
IPC: G06F12/1009 , G06F12/123
CPC classification number: G06F12/1009 , G06F12/123 , G06F2212/1021
Abstract: A processing device includes host interface circuitry to interact with a host system and an address translation circuit to handle address translation requests to the host system from host interface circuits. The address translation circuit includes a cache to store address translations associated with the address translation requests for future access by host interface circuits. A page request interface (PRI) handler tracks translation miss messages received from the host interface circuits, each translation miss message including a virtual address of a miss at the cache. The PRI handler removes duplicate translation miss messages having an identical virtual address and creates page miss requests from non-duplicate translation miss messages that are categorized into page request groups, each page request group corresponding to a host interface circuit of the host interface circuits. The PRI handler queues the page request groups to be sent to a translation agent of the host system.
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公开(公告)号：US11431629B2
公开(公告)日：2022-08-30
申请号：US16991376
申请日：2020-08-12
Applicant: Micron Technology, Inc.
Inventor： Aleksei Vlasov , Prateek Sharma , Yoav Weinberg , Scheheresade Virani , Bridget L. Mallak
Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.
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公开(公告)号：US20220222182A1
公开(公告)日：2022-07-14
申请号：US17711581
申请日：2022-04-01
Applicant: Micron Technology, Inc.
Inventor： Prateek Sharma
IPC: G06F12/1009 , G06F12/1045 , G06F9/54 , G06F9/455
Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.
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公开(公告)号：US20240385750A1
公开(公告)日：2024-11-21
申请号：US18785694
申请日：2024-07-26
Applicant: Micron Technology, Inc.
Inventor： Raja V.S. Halaharivi , Prateek Sharma
IPC: G06F3/06
Abstract: A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a firmware component of the memory device, a configuration setting based on an interrupt message associated with the first interface port; identifying an arbitration method for allocating one or more resources to the first interface port in a threshold period of time based on the configuration setting; and allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time, wherein the one or more resources includes memory access commands.
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Patent Agency Ranking
公开(公告)号：US20240168891A1
公开(公告)日：2024-05-23
申请号：US18517370
申请日：2023-11-22
Applicant: Micron Technology, Inc.
Inventor： Prateek Sharma , Raja V. S. Halaharivi , Sumangal Chakrabarty , Venkat R. Gaddam
IPC: G06F12/123 , G06F12/0882
CPC classification number: G06F12/123 , G06F12/0882 , G06F2212/1021
Abstract: A device includes an address translation circuit of host interface circuitry to handle address translation requests to a host system from a host queue interface circuit. The address translation circuit includes cache to store address translations associated with the address translation requests. The host queue interface circuit, coupled to the address translation circuit, is to: pause command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that missed at the cache; trigger a page request interface (PRI) handler to send a page miss request to a translation agent (TA) of the host, the page miss request including a virtual address of the address translation request; receive a restart message from the PRI handler upon the PRI handler receiving a page miss response from the TA; and restart command arbitration on the submission queue that was paused responsive to the restart message.
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公开(公告)号：US20240143515A1
公开(公告)日：2024-05-02
申请号：US18483790
申请日：2023-10-10
Applicant: Micron Technology, Inc.
Inventor： Sumangal Chakrabarty , Prateek Sharma , Raja V. S. Halaharivi , Yoav Weinberg , Di Hsien Ngu
IPC: G06F12/1081 , G06F13/30
CPC classification number: G06F12/1081 , G06F13/30 , G06F2212/6022 , G06F2212/657
Abstract: A system includes host interface circuitry to interact with a host system and that includes an address translation circuit, which includes request staging queues to buffer the address translation requests, each includes a virtual address and received from a host interface circuit. Pending response queues buffer respective address translation requests that are waiting for an address translation from the host system while maintaining an order as received within the request stage queues. Reordering buffers reorder address translations, which are to be supplied to the host interface circuits, according to the order maintained within the pending response queues, each address translation includes a physical address mapped to the virtual address of a corresponding address translation request. A cache stores multiple of the address translations, associated with the address translation requests, for future access by the host interface circuits.
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公开(公告)号：US11962500B2
公开(公告)日：2024-04-16
申请号：US17898018
申请日：2022-08-29
Applicant: Micron Technology, Inc.
Inventor： Aleksei Vlasov , Prateek Sharma , Yoav Weinberg , Scheheresade Virani , Bridget L. Mallak
Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.
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公开(公告)号：US11836511B2
公开(公告)日：2023-12-05
申请号：US16868643
申请日：2020-05-07
Applicant: Micron Technology, Inc.
Inventor： Prateek Sharma , Bridget L. Mallak , Kevin R. Duncan
CPC classification number: G06F9/45558 , G06F9/3836 , G06F9/44505 , G06F9/4818 , G06F11/3037 , G06F13/1605 , G06F2009/45583
Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.
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公开(公告)号：US20220417149A1
公开(公告)日：2022-12-29
申请号：US17898018
申请日：2022-08-29
Applicant: Micron Technology, Inc.
Inventor： Aleksei Vlasov , Prateek Sharma , Yoav Weinberg , Scheheresade Virani , Bridget L. Mallak
Abstract: A system includes a storage system and circuitry coupled to the storage system. The circuitry is configured to perform operations comprising determining a type of a received data packet, determining a destination of the received data packet, and determining whether the received data packet is of a particular type or has a particular destination. The operations further comprise, responsive to determining that the received data packet is of the particular type or has the particular destination, rerouting the received data packet from the particular destination to a register of the storage system.
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