公开(公告)号：US12216521B2

公开(公告)日：2025-02-04

申请号：US17887268

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya

IPC: G06F11/00 ,  G06F12/02

Abstract: Methods, systems, and devices for a common error protection buffer for multiple cursors are described. A memory device may receive a command to write data to a memory system. The memory device may assign portions of the data to respective pages of a first cursor and generate error protection data for the assigned data. The memory device may assign the generated error protection data to an error protection buffer common to multiple cursors, for example, by performing an combination operation. The memory device may increment a counter associated with the error protection buffer. The memory device may write a summary of contents of the error protection buffer and a position of each cursor related to the error protection data based on the counter satisfying a threshold. The memory device may perform a readback operation to facilitate garbage collection without losing error protection data.

公开(公告)号：US20250013379A1

公开(公告)日：2025-01-09

申请号：US18773967

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Jameer Mulani ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

Abstract: Techniques for memory operations are described. Indications of temperature levels at a memory device may be received, where each of the indications may be associated with a respective time point. Based on an indicated temperature level satisfying a first threshold, a derivative of a temperature of the memory device may be calculated using the indicated temperature levels. Based on calculating the derivative, a determination as to whether the derivative satisfies a second threshold may be determined. If the derivative satisfies the second threshold, operations for accessing the memory device may be modified. A second derivative of the temperature of the memory device may similarly be calculated and compared against a third threshold based on the indicated temperature level satisfying the first threshold. If the second derivative satisfies the third threshold, operations for accessing the memory device may be modified by a different amount.

公开(公告)号：US12032853B2

公开(公告)日：2024-07-09

申请号：US17584077

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Nicola Colella ,  Mani Raghavendra Aravapalli ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0679

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

公开(公告)号：US20240028215A1

公开(公告)日：2024-01-25

申请号：US17872590

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Rakeshkumar Dayabhai Vaghasiya

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0683

Abstract: Methods, systems, and devices for data storage during power state transition of a memory system are described. A memory system may receive a command indicating a transition from a first power state to a second power state or a third power state. Upon receiving the command, the memory system may write a first set of data to a volatile memory of the memory system. For example, the first set of data may be a snapshot or a copy of one or more elements of a second set of data. The memory system may flush the first set of data from the volatile memory to a non-volatile memory of the memory system. The memory system may transition from the first power state to the second power state or the third power state and read the snapshot from the volatile memory or the non-volatile memory upon transitioning back to the first power state.

公开(公告)号：US20230236762A1

公开(公告)日：2023-07-27

申请号：US17584077

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Nicola Colella ,  Mani Raghavendra Aravapalli ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

公开(公告)号：US20230214149A1

公开(公告)日：2023-07-06

申请号：US17677544

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Jameer Mulani ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Techniques for memory operations are described. Indications of temperature levels at a memory device may be received, where each of the indications may be associated with a respective time point. Based on an indicated temperature level satisfying a first threshold, a derivative of a temperature of the memory device may be calculated using the indicated temperature levels. Based on calculating the derivative, a determination as to whether the derivative satisfies a second threshold may be determined. If the derivative satisfies the second threshold, operations for accessing the memory device may be modified. A second derivative of the temperature of the memory device may similarly be calculated and compared against a third threshold based on the indicated temperature level satisfying the first threshold. If the second derivative satisfies the third threshold, operations for accessing the memory device may be modified by a different amount.