公开(公告)号：US20240061587A1

公开(公告)日：2024-02-22

申请号：US17892661

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Anilkumar Rameshbhai Sindhi ,  Dhruv Chauhan ,  Mani Raghavendra Aravapalli

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0679 ,  G06F3/0659

Abstract: Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.

公开(公告)号：US20240345743A1

公开(公告)日：2024-10-17

申请号：US18603033

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Nitul Gohain ,  Amiya Banerjee ,  Rakeshkumar Dayabhai Vaghasiya

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive polling for higher density storage are described. A controller of a memory system may identify a temperature of the memory device and select one or more polling parameters that are associated with identifying a status of the memory device based on a temperature of a memory system. In some cases, the controller may perform a polling operation according to the one or more polling parameters based on selecting the one or more polling parameters.

公开(公告)号：US12067281B2

公开(公告)日：2024-08-20

申请号：US17677544

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Jameer Mulani ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Techniques for memory operations are described. Indications of temperature levels at a memory device may be received, where each of the indications may be associated with a respective time point. Based on an indicated temperature level satisfying a first threshold, a derivative of a temperature of the memory device may be calculated using the indicated temperature levels. Based on calculating the derivative, a determination as to whether the derivative satisfies a second threshold may be determined. If the derivative satisfies the second threshold, operations for accessing the memory device may be modified. A second derivative of the temperature of the memory device may similarly be calculated and compared against a third threshold based on the indicated temperature level satisfying the first threshold. If the second derivative satisfies the third threshold, operations for accessing the memory device may be modified by a different amount.

公开(公告)号：US20240053900A1

公开(公告)日：2024-02-15

申请号：US17884422

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Anilkumar Rameshbhai Sindhi

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0629 ,  G06F3/0673 ,  G06F3/0659

Abstract: Methods, systems, and devices for sequential write operations using multiple memory dies are described. A memory system may be configured to support write operations that include writing respective subsets of a sequence of data to each first memory die of a set of multiple first memory dies, and then writing the sequence of data to a second memory die (e.g., based on reading the respective subsets of the sequence of data from the set of first memory dies). In some examples, such techniques may be implemented with memory dies having different memory cell storage densities. For example, the set of multiple first memory dies may be operated in accordance with relatively lower storage densities to leverage relatively faster access operations, whereas the second memory die may be operated in accordance with a relatively higher storage density to leverage relatively higher capacity.

公开(公告)号：US12248681B2

公开(公告)日：2025-03-11

申请号：US17884422

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Anilkumar Rameshbhai Sindhi

IPC: G06F3/06

Abstract: Methods, systems, and devices for sequential write operations using multiple memory dies are described. A memory system may be configured to support write operations that include writing respective subsets of a sequence of data to each first memory die of a set of multiple first memory dies, and then writing the sequence of data to a second memory die (e.g., based on reading the respective subsets of the sequence of data from the set of first memory dies). In some examples, such techniques may be implemented with memory dies having different memory cell storage densities. For example, the set of multiple first memory dies may be operated in accordance with relatively lower storage densities to leverage relatively faster access operations, whereas the second memory die may be operated in accordance with a relatively higher storage density to leverage relatively higher capacity.

公开(公告)号：US20240419360A1

公开(公告)日：2024-12-19

申请号：US18744998

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Nicola Colella ,  Mani Raghavendra Aravapalli ,  Anilkumar Rameshbhai Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

公开(公告)号：US20240281169A1

公开(公告)日：2024-08-22

申请号：US18441869

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Rakeshkumar Dayabhai Vaghasiya ,  Roberto Izzi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0605 ,  G06F3/0632 ,  G06F3/0679

Abstract: Methods, systems, and devices for reliable and efficient boot logical unit access are described. For instance, a memory device may receive a request to write data to a boot logical unit of the memory device. The memory device may update a parameter from a first value to a second value based on receiving the request, the second value indicating a first stage of a procedure for updating the boot logical unit. The memory device may write, to a block of memory in the memory device, the data based on the parameter indicating the first stage of the procedure. Additionally or alternatively, the memory device may read a value of the parameter as part of a power up procedure and may perform a boot procedure using either first data at the boot logical unit or second data at the block of memory based on reading the value of the parameter.

公开(公告)号：US20240168637A1

公开(公告)日：2024-05-23

申请号：US18506873

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Rakeshkumar Dayabhai Vaghasiya ,  Dhruv Chauhan ,  Anilkumar Rameshbhai Sindhi

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for prioritizing refresh operations of a memory system are described. In some instances, a memory system may refresh one or more production state awareness (PSA) blocks at power-on. In some cases, the PSA blocks that are refreshed may have relatively high bit error rates (BERs). For example, PSA blocks with relatively high BERs that are not refreshed may increase the risk of system failure or malfunction. Other PSA blocks may not be refreshed at power-on, and may instead be refreshed at a later time based on one or more criteria in order to prioritize refreshing the PSA blocks having relatively high BERs.

公开(公告)号：US20240054037A1

公开(公告)日：2024-02-15

申请号：US17887268

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya

IPC: G06F11/00 ,  G06F12/02

CPC classification number: G06F11/004 ,  G06F12/023 ,  G06F2212/1008 ,  G06F2212/2022

Abstract: Methods, systems, and devices for a common error protection buffer for multiple cursors are described. A memory device may receive a command to write data to a memory system. The memory device may assign portions of the data to respective pages of a first cursor and generate error protection data for the assigned data. The memory device may assign the generated error protection data to an error protection buffer common to multiple cursors, for example, by performing an combination operation. The memory device may increment a counter associated with the error protection buffer. The memory device may write a summary of contents of the error protection buffer and a position of each cursor related to the error protection data based on the counter satisfying a threshold. The memory device may perform a readback operation to facilitate garbage collection without losing error protection data.

公开(公告)号：US20250156296A1

公开(公告)日：2025-05-15

申请号：US18929369

申请日：2024-10-28

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Nicola Colella ,  Rakeshkumar Dayabhai Vaghasiya ,  Deping He

IPC: G06F11/34 ,  G06F9/50

Abstract: Methods, systems, and devices for memory allocation for a benchmark test are described. A memory system may be configured to allocate and deallocate portions of a volatile memory for specific uses based on detecting the occurrence of a benchmark testing operation. For example, the memory system may be configured to detect the occurrence of a benchmark testing operation based on the occurrence of one or more conditions. After detecting the benchmark testing operation, the memory system may deallocate a portion of the volatile memory associated with multiple-level cell accesses and may allocate (e.g., reallocate) the portion for storing additional logical-to-physical mappings.