公开(公告)号：US20240419360A1

公开(公告)日：2024-12-19

申请号：US18744998

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Nicola Colella ,  Mani Raghavendra Aravapalli ,  Anilkumar Rameshbhai Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

公开(公告)号：US12032853B2

公开(公告)日：2024-07-09

申请号：US17584077

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Nicola Colella ,  Mani Raghavendra Aravapalli ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0679

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

公开(公告)号：US20230236762A1

公开(公告)日：2023-07-27

申请号：US17584077

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Nicola Colella ,  Mani Raghavendra Aravapalli ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0619 ,  G06F3/0679

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

公开(公告)号：US20240289042A1

公开(公告)日：2024-08-29

申请号：US18438155

申请日：2024-02-09

Applicant: Micron Technology, Inc.

Inventor： Nikhil Birgade ,  Uday Bhasker V. Vudugandla ,  Mani Raghavendra Aravapalli

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0673

Abstract: Methods, systems, and devices for block replacement using combined blocks are described. A memory system may receive a command to perform an access operation on a block of the memory system. The memory system may determine whether a block pool includes a second block configured to replace the block based on a failure to perform the access operation. The memory system may generate a combined block for replacing the block based on determining an absence of the second block in the block pool. The combined block may be generated by combining two half good blocks (HGBs) in a same plane of the memory system as the block. In some cases, a second block pool may be generated and the combined block may be stored to the second block pool. The memory system may select the combined block from the second block pool and replace the block with the combined block.

公开(公告)号：US20240281254A1

公开(公告)日：2024-08-22

申请号：US18581273

申请日：2024-02-19

Applicant: Micron Technology, Inc.

Inventor： Sridhar Prudviraj Gunda ,  Mani Raghavendra Aravapalli ,  Ritesh Tiwari

IPC: G06F9/30

CPC classification number: G06F9/30185

Abstract: Methods, systems, and devices for overlay code retrieval from a host system are described. A memory system may determine that a set of code for execution by a processor of the memory system is absent from an executable memory of the processor. The memory system may prevent the processor from retrieving the set of code from a non-volatile memory of the memory system based on the set of code being designated for retrieval from a host system. The memory system may retrieve the set of code from a memory of a host system, instead of retrieving the set of code from the non-volatile memory, based on the set of code being designated for retrieval from the host system.

公开(公告)号：US20240061587A1

公开(公告)日：2024-02-22

申请号：US17892661

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Anilkumar Rameshbhai Sindhi ,  Dhruv Chauhan ,  Mani Raghavendra Aravapalli

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0679 ,  G06F3/0659

Abstract: Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.