公开(公告)号：US6144063A

公开(公告)日：2000-11-07

申请号：US47951

申请日：1998-03-25

Applicant: Geoffrey Choh-Fei Yeap ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Geoffrey Choh-Fei Yeap ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/72

CPC classification number: H01L21/28229 ,  H01L29/42364 ,  H01L29/6659

Abstract: A semiconductor device having a transistor or capacitor with an ultra-thin oxide, which is thinner than 10 angstrom in thickness, is manufactured by eliminating a gate oxidation step in the processing and using the polysilicon reoxidation step to create the ultra-thin gate oxide by diffusion after formation of the gate.

Abstract translation: 通过在处理中消除栅极氧化步骤并使用多晶硅再氧化步骤来制造具有厚度小于10埃的超薄氧化物的晶体管或电容器的半导体器件，以通过在多晶硅再氧化步骤中产生超薄栅极氧化物 形成门后扩散。

公开(公告)号：US6093594A

公开(公告)日：2000-07-25

申请号：US69879

申请日：1998-04-29

Applicant: Geoffrey Choh-Fei Yeap ,  Qi Xiang ,  Ming-Ren Lin

Inventor： Geoffrey Choh-Fei Yeap ,  Qi Xiang ,  Ming-Ren Lin

IPC: H01L21/8238

CPC classification number: H01L21/823864

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.

Abstract translation: 在通过N型掺杂剂注入形成栅极和栅极氧化物之后，处理超大规模CMOS集成电路半导体器件，以形成N型浅源极和漏极延伸结。 形成N型掺杂剂注入以形成N型深源极和漏极结的间隔物。 然后，较高温度的快速热退火优化NMOS源极和漏极延伸接合点和结，并且去除间隔物。 使用薄氧化物间隔物将P型掺杂剂注入位移到P型浅源极和漏极延伸结。 然后形成用于P型掺杂剂注入以形成P型深源极和漏极结的氮化物间隔物。 然后，第二较低温度的快速热退火独立地优化PMOS源极和漏极结，这些独立于NMOS源极和漏极结。

公开(公告)号：US06060364A

公开(公告)日：2000-05-09

申请号：US260880

申请日：1999-03-02

Applicant: Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

Inventor： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

Abstract translation: 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

公开(公告)号：US5960322A

公开(公告)日：1999-09-28

申请号：US994308

申请日：1997-12-19

Applicant: Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L29/6659 ,  H01L21/2652 ,  H01L29/6656 ,  Y10S438/917

Abstract: A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

Abstract translation: 制造超大规模集成电路半导体器件的方法抑制了硼激活快速热退火期间由于偏析到屏幕氧化物中的硼损失。 在用于超浅，源极和漏极延伸结的硼注入之前，使用屏幕氧化物的氮化将氮掺入屏幕氧化物层中。 在硼注入之前，使用第二屏蔽氧化物的第二次氮化用于更深，源极和漏极结。 该方法显着抑制了硼扩散和离开硅衬底的偏析，从而降低了整个源极和漏极结的串联电阻。

公开(公告)号：US5614765A

公开(公告)日：1997-03-25

申请号：US478319

申请日：1995-06-07

Applicant: Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

Inventor： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2221/1036 ,  H01L2924/0002

Abstract: An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.

Abstract translation: 用于集成电路和用于半导体器件的衬底载体的绝缘分隔的导线和连接通孔的互连级别，使用双镶嵌仅具有一个掩模图案以形成导电线和通孔。 导电线的掩模图案包含​​在绝缘材料中要形成通孔开口的横向扩大区域。 在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于 绝缘材料到其附魔。 保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。 侧壁用作通过开口蚀刻的自对准掩模。 保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。 在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。 在后者中，导电线路开口和通孔用相同的导电材料填充。

公开(公告)号：US08502283B2

公开(公告)日：2013-08-06

申请号：US11926655

申请日：2007-10-29

Applicant: Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US07498225B1

公开(公告)日：2009-03-03

申请号：US11428722

申请日：2006-07-05

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02672 ,  H01L29/785

Abstract: A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.

Abstract translation: 提供了一种用于形成半导体器件的鳍结构的方法，该半导体器件包括衬底和形成在衬底上的电介质层。 该方法包括蚀刻介电层以形成第一结构，在第一结构上沉积非晶硅层，以及蚀刻非晶硅层以形成与第一结构的第一和第二侧表面相邻的第二和第三鳍结构。 第二和第三鳍结构可以包括非晶硅材料。 该方法还包括在第二和第三鳍结构的上表面上沉积金属层，执行金属诱导结晶操作以将第二鳍和第三鳍结构的非晶硅材料转化成晶体硅材料，并且去除第一结构 。

公开(公告)号：US20090047770A1

公开(公告)日：2009-02-19

申请号：US12205361

申请日：2008-09-05

Applicant: Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

Inventor： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Abstract translation: 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温过程可以是ALD过程。

公开(公告)号：US07329582B1

公开(公告)日：2008-02-12

申请号：US11154785

申请日：2005-06-15

Applicant: James Pan ,  Jonathan Byron Smith ,  Ming-Ren Lin

Inventor： James Pan ,  Jonathan Byron Smith ,  Ming-Ren Lin

IPC: H01L21/335

CPC classification number: H01L29/41775 ,  H01L21/2652 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/288 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for fabricating a semiconductor device having an impurity doped region in a silicon substrate. The method comprises forming a metal silicide layer electrically contacting the impurity doped region and depositing a conductive layer overlying and electrically contacting the metal silicide layer. A dielectric layer is deposited overlying the conductive layer and an opening is etched through the dielectric layer to expose a portion of the conductive layer. A conductive material is selectively deposited to fill the opening and to electrically contact the impurity doped region.

Abstract translation: 提供了制造在硅衬底中具有杂质掺杂区的半导体器件的方法。 该方法包括形成与杂质掺杂区电接触的金属硅化物层，并沉积覆盖并电接触金属硅化物层的导电层。 沉积覆盖导电层的电介质层，并且通过电介质层蚀刻开口以暴露导电层的一部分。 选择性地沉积导电材料以填充开口并与杂质掺杂区域电接触。

公开(公告)号：US07306997B2

公开(公告)日：2007-12-11

申请号：US10986399

申请日：2004-11-10

Applicant: Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L21/336

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。