利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

103 条记录 (耗时 0.021 秒)

    Fast Mosfet with low-doped source/drain
    1.
    发明授权
    Fast Mosfet with low-doped source/drain 有权
    具有低掺杂源/漏极的快速Mosfet

    公开(公告)号：US06060364A

    公开(公告)日：2000-05-09

    申请号：US260880

    申请日：1999-03-02

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

    摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

    摘要翻译： 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

    Fast MOSFET with low-doped source/drain
    2.
    发明授权
    Fast MOSFET with low-doped source/drain 有权
    具有低掺杂源极/漏极的快速MOSFET

    公开(公告)号：US06238960B1

    公开(公告)日：2001-05-29

    申请号：US09483400

    申请日：2000-01-14

    申请人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    发明人： Witold P. Maszara ,  Srinath Krishnan ,  Ming-Ren Lin

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

    摘要： A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration. The lower doping concentration in the source/drain regions (62, 70) lowers the junction capacitance and provides improved control of floating body effects when employed in SOI type processes.

    摘要翻译： 形成晶体管（50,80）的方法（100）包括在半导体材料（56,122）的一部分上形成栅极氧化物（120），并形成掺杂浓度超过栅极的掺杂多晶硅膜（124） 氧化物（122）。 随后，蚀刻掺杂多晶硅膜（124）以形成覆盖半导体材料（56,122）中的沟道区域（58）的栅电极（52），其中栅电极（52）将半导体材料分离成第一 区域（60）和在其间具有沟道区（58）的第二区域（68）。 方法（100）还包括在第一区域（60）中形成漏极延伸区域（64）和在第二区域（68）中形成源极延伸区域（72），并且在第一区域 （60）和第二区域（68）中的源极区域（70）。 源极/漏极形成使得漏极和源极区域（62,70）具有小于多晶硅膜（124）掺杂浓度的掺杂剂浓度。 源极/漏极区域（62,70）中的较低掺杂浓度降低了结电容，并且当用于SOI类型工艺时，提供对浮体效应的改进的控制。

    Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects
    3.
    发明授权
    Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects 有权
    制造MOSFET器件结构的方法，其有助于缓解结电容和浮体效应

    公开(公告)号：US06204138B1

    公开(公告)日：2001-03-20

    申请号：US09260821

    申请日：1999-03-02

    申请人： Srinath Krishnan ,  Witold P. Maszara ,  Ming-Ren Lin

    发明人： Srinath Krishnan ,  Witold P. Maszara ,  Ming-Ren Lin

    IPC分类号： H01L21336

    CPC分类号： H01L29/78612 ,  H01L29/78621

    摘要： A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.

    摘要翻译： 提供了一种形成MOSFET器件的方法。 形成第一轻掺杂区域，第一轻掺杂区域包括器件的LDD延伸区域。 第二非常轻掺杂的区域至少部分地形成在第一轻掺杂区域的下方，第二非常轻掺杂的区域具有小于第一轻掺杂区域的掺杂剂浓度，并且第二极轻掺杂区域以较高能量 水平比第一轻掺杂区域。

    Fully silicided gate structure for FinFET devices
    6.
    发明授权
    Fully silicided gate structure for FinFET devices 有权
    FinFET器件的全硅化栅极结构

    公开(公告)号：US08008136B2

    公开(公告)日：2011-08-30

    申请号：US11379435

    申请日：2006-04-20

    申请人： Ming-Ren Lin ,  Witold P. Maszara ,  Haihong Wang ,  Bin Yu

    发明人： Ming-Ren Lin ,  Witold P. Maszara ,  Haihong Wang ,  Bin Yu

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

    摘要： A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

    摘要翻译： 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

    Method for and device having STI using partial etch trench bottom liner
    7.
    发明授权
    Method for and device having STI using partial etch trench bottom liner 有权
    使用局部蚀刻槽底衬的STI和器件的方法

    公开(公告)号：US06486038B1

    公开(公告)日：2002-11-26

    申请号：US09804360

    申请日：2001-03-12

    申请人： Witold P. Maszara ,  Ming-Ren Lin ,  Qi Xiang

    发明人： Witold P. Maszara ,  Ming-Ren Lin ,  Qi Xiang

    IPC分类号： H01L2176

    CPC分类号： H01L21/76264 ,  H01L21/76283

    摘要： A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of (a) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; (b) etching the silicon active layer to form an isolation trench wherein an unetched silicon layer at bottom of the isolation trench remains; (c) oxidizing the layer of silicon at the bottom of the isolation trench to a degree sufficient to oxidize through the layer of silicon at the bottom to the dielectric isolation layer; and (d) filling the isolation trench with a trench isolation material to form a shallow trench isolation structure.

    摘要翻译： 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：（a）提供具有硅有源层，介电隔离层和硅衬底的绝缘体上硅半导体晶片，其中 在介电隔离层上形成硅有源层，并在硅衬底上形成电介质隔离层; （b）蚀刻硅有源层以形成隔离沟槽，其中保留隔离沟槽底部的未蚀刻硅层; （c）将隔离沟槽的底部的硅层氧化至足以通过底部的硅层氧化成电介质隔离层的程度; 和（d）用沟槽隔离材料填充隔离沟槽以形成浅沟槽隔离结构。

    Suppression of boron segregation for shallow source and drain junctions in semiconductors
    8.
    发明授权
    Suppression of boron segregation for shallow source and drain junctions in semiconductors 失效
    抑制半导体中浅源极和漏极结的硼偏析

    公开(公告)号：US5960322A

    公开(公告)日：1999-09-28

    申请号：US994308

    申请日：1997-12-19

    申请人： Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

    发明人： Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6656 ,  Y10S438/917

    摘要： A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

    摘要翻译： 制造超大规模集成电路半导体器件的方法抑制了硼激活快速热退火期间由于偏析到屏幕氧化物中的硼损失。 在用于超浅，源极和漏极延伸结的硼注入之前，使用屏幕氧化物的氮化将氮掺入屏幕氧化物层中。 在硼注入之前，使用第二屏蔽氧化物的第二次氮化用于更深，源极和漏极结。 该方法显着抑制了硼扩散和离开硅衬底的偏析，从而降低了整个源极和漏极结的串联电阻。