公开(公告)号：US20090019415A1

公开(公告)日：2009-01-15

申请号：US12237246

申请日：2008-09-24

申请人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

发明人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。

公开(公告)号：US07448014B2

公开(公告)日：2008-11-04

申请号：US11370538

申请日：2006-03-08

申请人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

发明人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。

公开(公告)号：US20080256502A1

公开(公告)日：2008-10-16

申请号：US11733795

申请日：2007-04-11

申请人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

发明人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

摘要翻译： 电子电路布局细化方法和系统。 在电路布局区域上定义了一个大小相同的瓷砖网格。 电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。 执行用于放置在电网的多个瓦片内的电路的全局电路布线。 在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。 在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。 然后生成经调整的全局电路布线。

公开(公告)号：US07930669B2

公开(公告)日：2011-04-19

申请号：US12237246

申请日：2008-09-24

申请人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

发明人： Mark A. Lavin ,  Ruchir Puri ,  Louise H. Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。

公开(公告)号：US07685553B2

公开(公告)日：2010-03-23

申请号：US11733795

申请日：2007-04-11

申请人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

发明人： Evanthia Papadopoulou ,  Ruchir Puri ,  Mervyn Y. Tan ,  Louise H. Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.

摘要翻译： 电子电路布局细化方法和系统。 在电路布局区域上定义了一个大小相同的瓷砖网格。 电网的每个瓦片具有与放置在电路布局区域上的电路的关键面积估计相关联的相应临界面积估计量度。 执行用于放置在电网的多个瓦片内的电路的全局电路布线。 在对电路执行详细的电路布线之前执行分配给电网的各个瓦片的关键面积估计度量的估计。 在估计关键区域估计度量之后，调整全局电路路由，以便改进分配给网格的至少一个瓦片的相应临界区域估计度量。 然后生成经调整的全局电路布线。

公开(公告)号：US08261226B1

公开(公告)日：2012-09-04

申请号：US13187196

申请日：2011-07-20

申请人： Wiren Dale Becker ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Tingdong Zhou

发明人： Wiren Dale Becker ,  Ruchir Puri ,  Haoxing Ren ,  Hua Xiang ,  Tingdong Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/08

摘要： A scaled network flow graph is constructed, including a plurality of nodes and a plurality of edges. The plurality of nodes correspond to: (i) a pseudo device pin node for each pair of corresponding paired device pins; (ii) a pseudo bottom surface metal node for each pair of bottom surface metal pins on each of multiple routing layers; (iii) a source node connected to each of the pseudo device pin nodes; (iv) a sub-sink node for each pair of the paired bottom surface metal pins (each of the sub-sink nodes is connected to corresponding ones of the pseudo bottom surface metal nodes for each of the pairs of bottom surface metal pins on each of the multiple routing layers); and (v) a sink node connected to the sub-sink nodes. A capacity and a cost are assigned to each of the edges of the scaled network flow graph. A min-cost-max-flow technique is applied to the scaled network flow graph with the assigned capacities and costs to obtain an optimal flow solution. The paired bottom surface metal pins are assigned to the corresponding paired device pins, and routing connections there-between are assigned, in accordance with the optimal flow solution. A technique for use in the absence of pairing constraints is also provided, as is a pin-pairing technique.

摘要翻译： 构建了缩放的网络流程图，包括多个节点和多个边缘。 多个节点对应于：（i）每对对应的配对设备引脚的伪器件引脚节点; （ii）在多个路由层中的每一个上的每对底表面金属销的伪底面金属节点; （iii）连接到每个伪器件引脚节点的源节点; （iv）每对成对的底表面金属销（每个子汇点中的每一个连接到每个底面表面金属节点中的每个底表面金属节点的子汇点） 的多个路由层）; 和（v）连接到子汇点节点的汇聚节点。 容量和成本被分配给缩放的网络流程图的每个边缘。 最小成本最大流技术应用于具有分配容量和成本的缩放网络流图，以获得最佳流解决方案。 配对的底面金属针脚被分配给相应的配对器件引脚，并且根据最佳流量解决方案分配其间的路由连接。 还提供了在没有配对约束的情况下使用的技术，引脚配对技术也是如此。

公开(公告)号：US08117568B2

公开(公告)日：2012-02-14

申请号：US12237727

申请日：2008-09-25

申请人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

发明人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

摘要翻译： 方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的 之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。

公开(公告)号：US20100077372A1

公开(公告)日：2010-03-25

申请号：US12237727

申请日：2008-09-25

申请人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

发明人： Hua Xiang ,  Laertis Economikos ,  Mohammed F. Fayaz ,  Stephen E. Greco ,  Patricia A. O'Neil ,  Ruchir Puri

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/12 ,  Y02P90/265

摘要： Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

摘要翻译： 方法，设备和计算机程序产品提供了一种快速准确的模型，用于通过生成集成电路的设计来模拟集成电路制造过程中的化学机械抛光（CMP）步骤的影响; 同时产生集成电路的设计，使用简化模型来预测由在集成电路的制造期间使用的CMP处理步骤产生的集成电路的至少一个物理特性，其中简化模型是从执行的模拟导出的 之前的设计生成活动使用综合仿真程序来模拟物理特性; 使用预测的物理特性预测集成电路的性能; 并根据性能预测调整集成电路的设计。

公开(公告)号：US20070214446A1

公开(公告)日：2007-09-13

申请号：US11370538

申请日：2006-03-08

申请人： Mark Lavin ,  Ruchir Puri ,  Louise Trevillyan ,  Hua Xiang

发明人： Mark Lavin ,  Ruchir Puri ,  Louise Trevillyan ,  Hua Xiang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.

摘要翻译： 本发明提供了一种用于在芯片的设计阶段减轻互连变化的影响的方法，系统和程序产品。 在本发明的技术下，确定了芯片互连的全局和详细路由。 此后，执行虚拟填充估计和网格基金属密度估计。 然后，基于CMP模型，获得金属厚度的可变图。 基于可变图，识别对金属变化敏感的芯片的接线网（例如，由于CMP过程中的金属厚度损失/增益而不能满足定时闭合）。 然后将这些接线网重新布线以优化芯片。

公开(公告)号：US07533360B1

公开(公告)日：2009-05-12

申请号：US12177648

申请日：2008-07-22

申请人： Haoxing Ren ,  Hua Xiang ,  Tingdong Zhou

发明人： Haoxing Ren ,  Hua Xiang ,  Tingdong Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5072 ,  G06F2217/40

摘要： The present invention provides a method of performing BSM assignments for each routing layer typically having one BSM group (e.g. memory bus) per layer. Further, the present invention provides for routable BSM assignments. Further, the present invention provides a method for handling pair constraints providing for differential pairs to be placed close to each other. Further, the method of the present invention provides for simultaneous routing and pin assignments while honoring pair constraint concerns and optimizing wire length.

摘要翻译： 本发明提供了一种通常每层具有一个BSM组（例如存储器总线）的每个路由层执行BSM分配的方法。 此外，本发明提供可路由的BSM分配。 此外，本发明提供了一种用于处理提供用于彼此靠近放置的差分对的对约束的方法。 此外，本发明的方法提供同时布线和引脚分配，同时保证对约束关系并优化线长度。