公开(公告)号：US20060273266A1

公开(公告)日：2006-12-07

申请号：US11437594

申请日：2006-05-19

申请人： Moshe Preil ,  Jun Ye ,  James Wiley ,  Shauh-Teh Juang ,  Michael Gassner

发明人： Moshe Preil ,  Jun Ye ,  James Wiley ,  Shauh-Teh Juang ,  Michael Gassner

IPC分类号： G01N21/86

CPC分类号： G03F7/7085 ,  G01N2021/95676 ,  G03F1/84 ,  G03F7/7065 ,  G03F7/70666

摘要： One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.

摘要翻译： 用于在集成电路设计中检测，采样，分析和校正热点的方法的一个实施例允许识别每个设计层内的最弱图案，精确确定工艺的影响漂移对真实掩模的图案化性能 在真正的扫描仪中，以及最佳的过程校正，过程监控和RET改进，以优化集成电路器件的性能和产量。 将高速仿真与实际航空图像上的海量数据收集能力和/或特定感兴趣图像的抗蚀图像相结合，为最佳的RET实施和过程监控提供了一个完整的方法。

公开(公告)号：US20070050749A1

公开(公告)日：2007-03-01

申请号：US11466978

申请日：2006-08-24

申请人： Jun Ye ,  Moshe Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

发明人： Jun Ye ,  Moshe Preil ,  Xun Chen ,  Shauh-Teh Juang ,  James Wiley

IPC分类号： G06F17/50

CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70625

摘要： A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

摘要翻译： 公开了一种用于识别掩模的设备区域中的处理窗口签名图案的方法。 签名图案集合地提供了对一组工艺条件参数对光刻工艺的变化的唯一响应。 签名模式可以监控相关的过程状态参数，以了解过程漂移的迹象，分析过程状态参数，以确定哪些是限制和影响芯片产量，分析过程状态参数的变化以确定应反馈的校正 进入光刻过程或转发到蚀刻工艺，识别不按照预期将预期图案转印到晶片的特定掩模，以及鉴定相对于工艺条件参数的变化共享共同特性并以类似方式表现的掩模组， 将图案转移到晶片。

公开(公告)号：US08539388B2

公开(公告)日：2013-09-17

申请号：US12852664

申请日：2010-08-09

申请人： Chewn-Pu Jou ,  Ming-Tsun Lin ,  Fu-Lung Hsueh ,  Shauh-Teh Juang

发明人： Chewn-Pu Jou ,  Ming-Tsun Lin ,  Fu-Lung Hsueh ,  Shauh-Teh Juang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/505 ,  G06F2217/78

摘要： A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell.

摘要翻译： 描述布局系统，其包括布局单元，其被配置为基于用于指定处理节点的库单元为半导体芯片的掩模设计布置单元; 非关键路径确定单元，被配置为确定半导体芯片中的非关键路径; 细胞确定单元，被配置为确定所述掩模设计中形成所述非关键路径的一部分的一组细胞，并确定所述细胞组中的至少一个的相应库细胞; 文库细胞修饰单元，被配置为修饰一个或多个相应的文库细胞以形成相应的修饰的文库细胞; 以及细胞置换单元，被配置为用形成所述非关键路径的一部分的掩模设计中的所述细胞组中的库单元替换相应的修改的库单元。