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    Display panel
    11.
    发明授权
    Display panel 有权

    公开(公告)号：US09972271B2

    公开(公告)日：2018-05-15

    申请号：US15152575

    申请日：2016-05-12

    Applicant: Novatek Microelectronics Corp.

    Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

    IPC: G09G3/36

    CPC classification number: G09G3/3685 ,  G02F1/13 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/02 ,  G09G2320/0223

    Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

    DISPLAY PANEL
    13.
    发明申请
    DISPLAY PANEL 有权

    公开(公告)号：US20170330527A1

    公开(公告)日：2017-11-16

    申请号：US15152575

    申请日：2016-05-12

    Applicant: Novatek Microelectronics Corp.

    Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng

    IPC: G09G3/36

    CPC classification number: G09G3/3685 ,  G02F1/13 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/02 ,  G09G2320/0223

    Abstract: A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.

    Panel driver IC and cooling method thereof
    15.
    发明授权
    Panel driver IC and cooling method thereof 有权
    面板驱动IC及其冷却方法

    公开(公告)号：US09569989B2

    公开(公告)日：2017-02-14

    申请号：US13928376

    申请日：2013-06-26

    Applicant: Novatek Microelectronics Corp.

    Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chieh-An Lin

    IPC: G09G3/00

    CPC classification number: G09G3/00 ,  G09G2300/0838 ,  G09G2300/0871 ,  G09G2310/0213 ,  G09G2310/0289 ,  G09G2330/045

    Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.

    Abstract translation: 提供面板驱动器集成电路（IC）和面板驱动器IC的冷却方法。 面板驱动器IC包括数据编码器，电平转换器，数模转换器（DAC），重排电路和输出缓冲器。 数据编码器接收并选择性地改变用于输出到电平移位器的原始数据。 电平移位器的输入端子和输出端子分别耦合到数据编码器的输出端子和DAC的数据输入端子。 重排电路的输出端分别耦合到DAC的参考电压输入端，以提供不同的参考电压。 重排电路根据数据编码器的操作相应地重新排列参考电压的顺序。 输出缓冲器的输入端耦合到DAC的输出端。

    DISPLAY APPARATUS AND DRIVING METHOD THEREOF
    16.
    发明申请
    DISPLAY APPARATUS AND DRIVING METHOD THEREOF 审中-公开
    显示装置及其驱动方法

    公开(公告)号：US20170018242A1

    公开(公告)日：2017-01-19

    申请号：US14801855

    申请日：2015-07-17

    Applicant: Novatek Microelectronics Corp.

    Inventor： Chieh-An Lin ,  Jhih-Siou Cheng ,  Po-Hsiang Fang ,  Po-Yu Tseng ,  Ju-Lin Huang ,  Yi-Chuan Liu

    IPC: G09G3/36

    CPC classification number: G09G3/3688 ,  G09G2310/0251

    Abstract: A display apparatus and a driving method of the same are provided. The display apparatus includes a display panel, a gate driver circuit, and a source driver circuit. During a functional sub-period of a frame period, the gate driver circuit simultaneously drives a plurality of gate lines, and the source driver circuit drives a plurality of source lines, so as to perform a function on a plurality of pixels connected to the gate lines. In a scan sub-period of the frame period, the gate driver circuit drives the gate lines according to a scan sequence, and the source driver circuit correspondingly drives the source lines according to the scan sequence of the gate driver circuit in the first scan sub-period, so as to display an image.

    Abstract translation: 提供了一种显示装置及其驱动方法。 显示装置包括显示面板，栅极驱动电路和源极驱动电路。 在帧周期的功能子周期期间，栅极驱动器电路同时驱动多条栅极线，并且源极驱动电路驱动多条源极线，以便对连接到栅极的多个像素执行功能 线条。 在帧周期的扫描子周期中，栅极驱动电路根据扫描序列驱动栅极线，并且源极驱动电路根据第一扫描子像素中的栅极驱动电路的扫描顺序相应地驱动源极线 周期，以便显示图像。

    Image display system and display driving module
    17.
    发明授权
    Image display system and display driving module 有权
    图像显示系统和显示驱动模块

    公开(公告)号：US09514666B2

    公开(公告)日：2016-12-06

    申请号：US14645434

    申请日：2015-03-12

    Applicant: Novatek Microelectronics Corp.

    Inventor： Ju-Lin Huang ,  Jhih-Siou Cheng ,  Chun-Yung Cho ,  Chia-En Wu

    IPC: G09G5/00 ,  G09G3/20

    CPC classification number: G09G3/20 ,  G09G2330/04 ,  G09G2330/06

    Abstract: A display driving module including a driving circuit portion and a non-driving circuit portion is provided. The driving circuit portion is controlled by a system circuit block. The driving circuit portion includes driving channels for driving a display panel. First ESD protection devices are disposed in the driving circuit portion corresponding to the driving channels for providing at least one discharge path. The non-driving circuit portion electrically connects the system circuit block, the driving circuit portion and the display panel. At least one of second ESD protection devices is disposed in at least one of the driving circuit portion, the non-driving circuit portion, the system circuit block and the display panel corresponding to the first ESD protection devices. The second ESD protection devices cooperate with the first ESD protection devices to provide the discharge path. An image display system including the foregoing display driving module is also provided.

    Abstract translation: 提供了包括驱动电路部分和非驱动电路部分的显示驱动模块。 驱动电路部分由系统电路块控制。 驱动电路部分包括用于驱动显示面板的驱动通道。 第一ESD保护装置设置在对应于驱动通道的驱动电路部分中，用于提供至少一个放电路径。 非驱动电路部分电连接系统电路块，驱动电路部分和显示面板。 至少一个第二ESD保护器件设置在驱动电路部分，非驱动电路部分，系统电路块和对应于第一ESD保护器件的显示面板中的至少一个中。 第二ESD保护装置与第一ESD保护装置配合以提供放电路径。 还提供了包括上述显示驱动模块的图像显示系统。

    CHIP PACKAGE
    18.
    发明申请
    CHIP PACKAGE 审中-公开
    芯片包装

    公开(公告)号：US20150262943A1

    公开(公告)日：2015-09-17

    申请号：US14726613

    申请日：2015-06-01

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

    IPC: H01L23/60 ,  H02H9/02 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

    CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

    Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

    Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

    Chip package
    19.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US09048243B2

    公开(公告)日：2015-06-02

    申请号：US13674903

    申请日：2012-11-12

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

    IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/60 ,  H05K9/00 ,  H01L25/065

    CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

    Abstract: A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.

    Abstract translation: 芯片封装结构包括封装体，第一引线和第二引线。 嵌入在封装体内的元件包括具有至少一个第一连接端子，至少一个ESD保护电路的至少一个第二连接端子，至少一个第三连接端子和至少一个互连结构的芯电路。 互连结构电连接到第二连接端子和第三连接端子。 封装主体上的第一引线电连接到第二连接端子和外部电路。 封装体上的第二引线电连接第一连接端子和第三连接端子。 第二个引线和第一个引线在结构上是分开的。

    LEVEL SHIFTING CIRCUIT WITH DYNAMIC CONTROL
    20.
    发明申请
    LEVEL SHIFTING CIRCUIT WITH DYNAMIC CONTROL 有权
    水平移动电路与动态控制

    公开(公告)号：US20140015587A1

    公开(公告)日：2014-01-16

    申请号：US13792245

    申请日：2013-03-11

    Applicant: NOVATEK MICROELECTRONICS CORP

    Inventor： Cheng-Hung Chen ,  Ju-Lin Huang ,  Keko-Chun Liang

    IPC: H03K3/012

    CPC classification number: H03K3/012 ,  H03K3/356182

    Abstract: A level shifting circuit with dynamic control includes a dynamic controller and a level shifter. The dynamic controller outputs a dynamic voltage and an output data signal. The level shifter under control by the dynamic controller includes an input signal receiver, an output signal generator, and a bias current controller, which are coupled in series between a ground voltage and a high level voltage. The input signal receiver receives the output data signal of the dynamic controller and the output signal generator produces a level-shifted data signal according to the input data signal. The bias current controller controlled by the dynamic voltage is at a first current-output capability when the level-shifted data signal is at a stable stage and at a second current-output capability when the level-shifted data signal is at an unstable stage. The first current-output capability is greater than the second current-output capability.

    Abstract translation: 具有动态控制的电平移动电路包括动态控制器和电平转换器。 动态控制器输出动态电压和输出数据信号。 由动态控制器控制的电平移位器包括输入信号接收器，输出信号发生器和偏置电流控制器，它们串联在接地电压和高电平电压之间。 输入信号接收器接收动态控制器的输出数据信号，输出信号发生器根据输入数据信号产生电平移位数据信号。 当电平移位数据信号处于不稳定阶段时，当电平移位数据信号处于稳定级并处于第二电流输出能力时，由动态电压控制的偏置电流控制器处于第一电流输出能力。 第一个电流输出能力大于第二个电流输出能力。

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