公开(公告)号：US08866528B2

公开(公告)日：2014-10-21

申请号：US13668110

申请日：2012-11-02

Applicant: NVIDIA Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: H03K3/289

CPC classification number: H03K3/356156 ,  G01R31/318541 ,  H03K3/356121

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract translation: 双触发器电路将两个或更多个触发器子电路组合成单个电路。 触发器电路包括第一触发器子电路和第二触发器子电路。 第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号， 被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。 第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。 第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定输入信号传送到第二输出信号。

公开(公告)号：US20140167828A1

公开(公告)日：2014-06-19

申请号：US13715969

申请日：2012-12-14

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Abstract translation: 小区域低功率数据保留触发器。 根据本发明的第一实施例，电路包括耦合到数据保持锁存器的主锁存器。 数据保持锁存器被配置为作为从锁存器操作到主锁存器，以在正常操作期间实现主从触发器。 数据保持锁存器配置为在主器件锁存器掉电时，在低功耗数据保持模式期间保持主从触发器的输出值。 单个控制输入被配置为在正常操作和低功率数据保持模式之间进行选择。 电路可以独立于第三锁存器。