公开(公告)号：US20140125377A1

公开(公告)日：2014-05-08

申请号：US13668110

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: H03K19/0175 ,  H03K19/00

CPC classification number: H03K3/356156 ,  G01R31/318541 ,  H03K3/356121

Abstract: A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.

Abstract translation: 双触发器电路将两个或更多个触发器子电路组合成单个电路。 触发器电路包括第一触发器子电路和第二触发器子电路。 第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号， 被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。 第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。 第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定的输入信号传送到第二输出信号。

公开(公告)号：US09110141B2

公开(公告)日：2015-08-18

申请号：US13668143

申请日：2012-11-02

Applicant: NVIDIA Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318541 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318594

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract translation: 扫描触发电路包括扫描输入子电路和选择子电路。 扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号 信号在两个不同的逻辑电平之间。 选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相版本输出为第一选择 输入信号。

公开(公告)号：US08988123B2

公开(公告)日：2015-03-24

申请号：US13715969

申请日：2012-12-14

Applicant: NVIDIA Corporation

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0375

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Abstract translation: 小区域低功率数据保留触发器。 根据本发明的第一实施例，电路包括耦合到数据保持锁存器的主锁存器。 数据保持锁存器被配置为作为从锁存器操作到主锁存器，以在正常操作期间实现主从触发器。 数据保持锁存器配置为在主器件锁存器掉电时，在低功耗数据保持模式期间保持主从触发器的输出值。 单个控制输入被配置为在正常操作和低功率数据保持模式之间进行选择。 电路可以独立于第三锁存器。

公开(公告)号：US20140129887A1

公开(公告)日：2014-05-08

申请号：US13668143

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318594

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract translation: 扫描触发电路包括扫描输入子电路和选择子电路。 扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号 信号在两个不同的逻辑电平之间。 选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相形式输出为第一选择 输入信号。

公开(公告)号：US20140084984A1

公开(公告)日：2014-03-27

申请号：US13626100

申请日：2012-09-25

Applicant: NVIDIA CORPORATION

Inventor： Hank Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: H03L5/00

CPC classification number: H03K19/017509 ,  H03K19/018507

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract translation: 本文提供了一种电压电平移位器，包括电压电平移位器的装置和在输入和输出电力域之间转换电压的方法。 在一个实施例中，电压电平移位器包括：（1）被配置为从输入功率域接收数据信号的输入电路和来自输出功率域的掉电信号，以及（2）耦合到输入电路的转换电路和 被配置为接收所述数据信号和所述掉电信号的反相信号，其中所述输入电路和所述转换电路都被配置为连接到所述输出功率域的电源电压作为电源。

公开(公告)号：US10181842B2

公开(公告)日：2019-01-15

申请号：US14945377

申请日：2015-11-18

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Lingfei Deng ,  Hwong-Kwo Lin

IPC: H03K3/356 ,  H03K3/037

Abstract: A flip-flop element is configured to include FinFET technology transistors with a mix of threshold voltage levels. The data input path includes FinFET transistors configured with high voltage thresholds (HVT). The clock input path includes transistors configured with standard voltage thresholds (SVT). By including FinFET transistors with SVT thresholds in the clock signal path, the Miller capacitance of the clock signal path is reduced relative to HVT FinFET transistors, leading to lower rise time and correspondingly lower hold time. By including HVT threshold devices in the data input path, the flip-flop element attains high speed and low power operation. By including SVT threshold devices in the clock signal path, the flip-flop element achieves faster switching times in the clock signal path.

公开(公告)号：US09842631B2

公开(公告)日：2017-12-12

申请号：US13715991

申请日：2012-12-14

Applicant: NVIDIA Corporation

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: G11C7/12 ,  G11C11/4091

CPC classification number: G11C7/12 ,  G11C11/4091

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

公开(公告)号：US20140169108A1

公开(公告)日：2014-06-19

申请号：US13715991

申请日：2012-12-14

Applicant: NVIDIA CORPORATION

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4091

Abstract: Mitigating external influences on long signal lines. In accordance with an embodiment of the present invention, a column of a memory array includes first and second transistors configured to pull up the bit line of the column. The column includes a third transistor configured to selectively pull up the bit line of the column responsive to a level of the inverted bit line of the column and a fourth transistor configured to selectively pull up the inverted bit line of the column responsive to a level of the bit line of the column. The column further includes fifth and sixth transistors configured to selectively pull up the bit line and inverted bit line of the column responsive to the clamp signal and a seventh transistor configured to selectively couple the bit line of the column and the inverted bit line of the column responsive to the clamp signal.

Abstract translation: 减轻对长信号线的外部影响。 根据本发明的实施例，存储阵列的列包括被配置为上拉列的位线的第一和第二晶体管。 该列包括第三晶体管，其被配置为响应于该列的反相位线的电平有选择地上拉该列的位线;以及第四晶体管，其被配置为响应于该列的反相位线选择性地上拉该反相位线 列的位线。 该列还包括第五和第六晶体管，其被配置为响应钳位信号选择性地上拉该列的位线和反相位线;以及第七晶体管，被配置为选择性地耦合该列的位线和该列的反相位线 响应钳位信号。

公开(公告)号：US10931266B2

公开(公告)日：2021-02-23

申请号：US14456805

申请日：2014-08-11

Applicant: NVIDIA CORPORATION

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037

Abstract: A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.

公开(公告)号：US09071240B2

公开(公告)日：2015-06-30

申请号：US13626100

申请日：2012-09-25

Applicant: Nvidia Corporation

Inventor： Hank Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: H03L5/00 ,  H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/017509 ,  H03K19/018507

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract translation: 本文提供了一种电压电平移位器，包括电压电平移位器的装置和在输入和输出电力域之间转换电压的方法。 在一个实施例中，电压电平移位器包括：（1）被配置为从输入功率域接收数据信号的输入电路和来自输出功率域的掉电信号，以及（2）耦合到输入电路的转换电路和 被配置为接收所述数据信号和所述掉电信号的反相信号，其中所述输入电路和所述转换电路都被配置为连接到所述输出功率域的电源电压作为电源。