公开(公告)号：US20170234927A1

公开(公告)日：2017-08-17

申请号：US15257781

申请日：2016-09-06

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/28 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318572

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

公开(公告)号：US09542992B2

公开(公告)日：2017-01-10

申请号：US13865281

申请日：2013-04-18

Applicant: NVIDIA CORPORATION

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Fei Song ,  Xi Zhang ,  Haiyan Gong

IPC: G11C11/412

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.

Abstract translation: 静态随机存取存储器（SRAM）单元包括被配置为在存储节点中存储数据位的存储单元。 SRAM单元还包括耦合到存储单元的存取单元。 访问单元被配置为当字线被断言时将电流传送到存储节点。 SRAM单元进一步包括行标头，其被配置为当字线未被断言时提供来自电源的电流，并且当字线被断言时不提供来自电源的电流。 SRAM单元进一步包括列头，其配置成当写入列线未被置位时提供来自电源的电流，并且当写入列线被断言时不提供来自电源的电流。

公开(公告)号：US09110141B2

公开(公告)日：2015-08-18

申请号：US13668143

申请日：2012-11-02

Applicant: NVIDIA Corporation

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318541 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318594

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract translation: 扫描触发电路包括扫描输入子电路和选择子电路。 扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号 信号在两个不同的逻辑电平之间。 选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相版本输出为第一选择 输入信号。

公开(公告)号：US20130278315A1

公开(公告)日：2013-10-24

申请号：US13921138

申请日：2013-06-18

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Ge Yang

IPC: H03K3/36

CPC classification number: H03K3/36 ,  H03K3/012 ,  H03K3/356121

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the dock.

Abstract translation: 本发明的一个实施例提出了一种技术，用于使用完全静态且对制造工艺变化不敏感的双触发低能量触发器电路来捕获和存储输入信号电平的技术。 双触发低能触发器电路仅向时钟信号提供三个晶体管栅极负载，并且当输入信号保持恒定时，内部节点都不会切换。 时钟信号之一可以是低频“保持时钟”，其比输入到两个晶体管栅极的另外两个时钟信号频率更低。 输出信号Q在上升时钟沿使用分离的触发子电路设置或复位。 当时钟信号为低电平时，设置或复位可能被布防，并且在基座的上升沿触发置位或复位。

公开(公告)号：US09525401B2

公开(公告)日：2016-12-20

申请号：US14644637

申请日：2015-03-11

Applicant: NVIDIA Corporation

Inventor： Xi Zhang ,  Hwong-Kwo Lin ,  Ge Yang ,  Lingfei Deng

IPC: H03K3/00 ,  H03K3/012 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/0372 ,  H03K19/21

Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.

Abstract translation: 低时钟电源触发器。 根据本发明的第一实施例，触发器电子电路包括以触发器配置耦合到从锁存器的主锁存器。 触发器电子电路还包括用于将输入与主锁存器的输入与从锁存器的输出进行比较的时钟控制电路，并且响应于比较，当触发器电路电路将时钟信号阻塞到主锁存器和从锁存器时， 触发器电子电路处于静止状态。

公开(公告)号：US08988123B2

公开(公告)日：2015-03-24

申请号：US13715969

申请日：2012-12-14

Applicant: NVIDIA Corporation

Inventor： Ge Yang ,  Hwong-Kwo Lin ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0375

Abstract: Small area low power data retention flop. In accordance with a first embodiment of the present invention, a circuit includes a master latch coupled to a data retention latch. The data retention latch is configured to operate as a slave latch to the master latch to implement a master-slave flip flop during normal operation. The data retention latch is configured to retain an output value of the master-slave flip flop during a low power data retention mode when the master latch is powered down. A single control input is configured to select between the normal operation and the low power data retention mode. The circuit may be independent of a third latch.

Abstract translation: 小区域低功率数据保留触发器。 根据本发明的第一实施例，电路包括耦合到数据保持锁存器的主锁存器。 数据保持锁存器被配置为作为从锁存器操作到主锁存器，以在正常操作期间实现主从触发器。 数据保持锁存器配置为在主器件锁存器掉电时，在低功耗数据保持模式期间保持主从触发器的输出值。 单个控制输入被配置为在正常操作和低功率数据保持模式之间进行选择。 电路可以独立于第三锁存器。

公开(公告)号：US20150028927A1

公开(公告)日：2015-01-29

申请号：US13949252

申请日：2013-07-24

Applicant: NVIDIA Corporation

Inventor： Ilyas Elkin ,  Ge Yang

IPC: H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372

Abstract: A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

Abstract translation: 触发器电路可以包括主锁存器和从锁存器。 每个锁存器可以具有透明模式和存储模式。 当主锁存器处于透明模式时，从锁存器可能处于存储模式; 反之亦然。 时钟信号可以通过一对时钟门控上拉晶体管和一对时钟门控的下拉晶体管来控制每个锁存器的模式，总共四个时钟门控晶体管。 时钟门控晶体管可以由主锁存器和从锁存器共享。 当共享时，可能需要更少的时钟门控晶体管，而不是被共享。 由于寄生电容的充电和放电，时钟门控晶体管可能具有寄生电容并且当经受变化的时钟信号时消耗功率。 因此，具有更少的时钟门控晶体管可以减少触发器电路消耗的功率。

公开(公告)号：US20140129887A1

公开(公告)日：2014-05-08

申请号：US13668143

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Hwong-Kwo Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Ting-Hsiang Chu

IPC: G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318594

Abstract: A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

Abstract translation: 扫描触发电路包括扫描输入子电路和选择子电路。 扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号 信号在两个不同的逻辑电平之间。 选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相形式输出为第一选择 输入信号。

公开(公告)号：US20140084984A1

公开(公告)日：2014-03-27

申请号：US13626100

申请日：2012-09-25

Applicant: NVIDIA CORPORATION

Inventor： Hank Lin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu ,  Haiyan Gong

IPC: H03L5/00

CPC classification number: H03K19/017509 ,  H03K19/018507

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract translation: 本文提供了一种电压电平移位器，包括电压电平移位器的装置和在输入和输出电力域之间转换电压的方法。 在一个实施例中，电压电平移位器包括：（1）被配置为从输入功率域接收数据信号的输入电路和来自输出功率域的掉电信号，以及（2）耦合到输入电路的转换电路和 被配置为接收所述数据信号和所述掉电信号的反相信号，其中所述输入电路和所述转换电路都被配置为连接到所述输出功率域的电源电压作为电源。

公开(公告)号：US10931266B2

公开(公告)日：2021-02-23

申请号：US14456805

申请日：2014-08-11

Applicant: NVIDIA CORPORATION

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang ,  Jiani Yu

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/037

Abstract: A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.